44076c9822
Move the emission of the checks performed on the authenticated LR value during tail calls to AArch64AsmPrinter class, so that different checker sequences can be reused by pseudo instructions expanded there. This adds one more option to AuthCheckMethod enumeration, the generic XPAC variant which is not restricted to checking the LR register.
114 lines
4.6 KiB
LLVM
114 lines
4.6 KiB
LLVM
; RUN: llc -mtriple aarch64 -o - %s \
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; RUN: -aarch64-authenticated-lr-check-method=xpac-hint \
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; RUN: -stop-before=aarch64-ptrauth \
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; RUN: | FileCheck --check-prefix=MIR %s
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; RUN: llc -mtriple aarch64 -o - %s -asm-verbose=0 \
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; RUN: -aarch64-authenticated-lr-check-method=xpac-hint \
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; RUN: | FileCheck --check-prefix=ASM %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
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;; Test that expansion of AUTH_TCRETURN does not crash due to unavailability of
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;; neither x16 nor x17 as a scratch register.
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define i32 @test_scratch_reg_nobti(ptr %callee, ptr %addr) #0 {
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entry:
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;; Force spilling of LR
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tail call void asm sideeffect "", "~{lr}"()
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;; Clobber x0-x15 and x18-x29. This is rather fragile but it was observed to
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;; trick regalloc into allocating both x16 and x17 as inputs of AUTH_TCRETURN.
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tail call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15}"()
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tail call void asm sideeffect "", "~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp}"()
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%addr.i = ptrtoint ptr %addr to i64
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%call = tail call i32 %callee() #1 [ "ptrauth"(i32 0, i64 %addr.i) ]
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ret i32 %call
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}
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;; Ensure the specific tail call pseudo instruction is used.
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; MIR-LABEL: name: test_scratch_reg_nobti
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; MIR: AUTH_TCRETURN{{ }}
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;
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; ASM-LABEL: test_scratch_reg_nobti:
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; ASM-NEXT: pacibsp
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; ASM-NEXT: sub sp, sp, #112
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; ASM-NEXT: stp x29, x30, [sp, #16]
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; ASM-NEXT: mov x16, x1
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; ASM-NEXT: stp x28, x27, [sp, #32]
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; ASM-NEXT: stp x26, x25, [sp, #48]
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; ASM-NEXT: stp x24, x23, [sp, #64]
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; ASM-NEXT: stp x22, x21, [sp, #80]
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; ASM-NEXT: stp x20, x19, [sp, #96]
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; ASM-NEXT: str x0, [sp, #8]
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; ASM-NEXT: //APP
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; ASM-NEXT: //NO_APP
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; ASM-NEXT: //APP
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; ASM-NEXT: //NO_APP
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; ASM-NEXT: //APP
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; ASM-NEXT: //NO_APP
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; ASM-NEXT: ldr x0, [sp, #8]
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; ASM-NEXT: ldp x20, x19, [sp, #96]
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; ASM-NEXT: ldp x22, x21, [sp, #80]
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; ASM-NEXT: ldp x24, x23, [sp, #64]
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; ASM-NEXT: ldp x26, x25, [sp, #48]
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; ASM-NEXT: ldp x28, x27, [sp, #32]
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; ASM-NEXT: ldp x29, x30, [sp, #16]
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; ASM-NEXT: add sp, sp, #112
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; ASM-NEXT: autibsp
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; ASM-NEXT: eor x17, x30, x30, lsl #1
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; ASM-NEXT: tbz x17, #62, .Lauth_success_0
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; ASM-NEXT: brk #0xc471
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; ASM-NEXT: .Lauth_success_0:
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; ASM-NEXT: braa x0, x16
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; ASM-NEXT: .Lfunc_end0:
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;; The same for AUTH_TCRETURN_BTI.
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define i32 @test_scratch_reg_bti(ptr %callee, ptr %addr) "branch-target-enforcement" #0 {
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entry:
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;; Force spilling of LR
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tail call void asm sideeffect "", "~{lr}"()
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;; Clobber x0-x15 and x18-x29. This is rather fragile but it was observed to
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;; trick regalloc into allocating both x16 and x17 as inputs of AUTH_TCRETURN_BTI.
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tail call void asm sideeffect "", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15}"()
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tail call void asm sideeffect "", "~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp}"()
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%addr.i = ptrtoint ptr %addr to i64
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%call = tail call i32 %callee() #1 [ "ptrauth"(i32 0, i64 %addr.i) ]
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ret i32 %call
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}
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;; Ensure the specific tail call pseudo instruction is used.
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; MIR-LABEL: name: test_scratch_reg_bti
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; MIR: AUTH_TCRETURN_BTI
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;
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; ASM-LABEL: test_scratch_reg_bti:
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; ASM-NEXT: pacibsp
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; ASM-NEXT: sub sp, sp, #112
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; ASM-NEXT: stp x29, x30, [sp, #16]
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; ASM-NEXT: mov x16, x0
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; ASM-NEXT: stp x28, x27, [sp, #32]
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; ASM-NEXT: stp x26, x25, [sp, #48]
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; ASM-NEXT: stp x24, x23, [sp, #64]
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; ASM-NEXT: stp x22, x21, [sp, #80]
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; ASM-NEXT: stp x20, x19, [sp, #96]
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; ASM-NEXT: str x1, [sp, #8]
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; ASM-NEXT: //APP
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; ASM-NEXT: //NO_APP
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; ASM-NEXT: //APP
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; ASM-NEXT: //NO_APP
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; ASM-NEXT: //APP
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; ASM-NEXT: //NO_APP
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; ASM-NEXT: ldr x0, [sp, #8]
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; ASM-NEXT: ldp x20, x19, [sp, #96]
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; ASM-NEXT: ldp x22, x21, [sp, #80]
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; ASM-NEXT: ldp x24, x23, [sp, #64]
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; ASM-NEXT: ldp x26, x25, [sp, #48]
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; ASM-NEXT: ldp x28, x27, [sp, #32]
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; ASM-NEXT: ldp x29, x30, [sp, #16]
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; ASM-NEXT: add sp, sp, #112
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; ASM-NEXT: autibsp
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; ASM-NEXT: eor x17, x30, x30, lsl #1
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; ASM-NEXT: tbz x17, #62, .Lauth_success_1
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; ASM-NEXT: brk #0xc471
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; ASM-NEXT: .Lauth_success_1:
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; ASM-NEXT: braa x16, x0
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; ASM-NEXT: .Lfunc_end1:
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attributes #0 = { nounwind "ptrauth-auth-traps" "ptrauth-calls" "ptrauth-returns" "target-features"="+pauth" }
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