db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
107 lines
3.5 KiB
LLVM
107 lines
3.5 KiB
LLVM
; Test shrink wrapping placement is correct with respect to calls to llvm.{stacksave,stackrestore}
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; void f(int n, int x[]) {
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; if (n < 0)
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; return;
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;
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; int a[n];
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;
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; for (int i = 0; i < n; i++)
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; a[i] = x[n - i - 1];
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;
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; for (int i = 0; i < n; i++)
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; x[i] = a[i] + 1;
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; }
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;
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; RUN: llc -mtriple aarch64-linux %s -o - | FileCheck %s
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define dso_local void @f(i32 %n, ptr nocapture %x) uwtable {
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entry:
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%cmp = icmp slt i32 %n, 0
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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%0 = zext i32 %n to i64
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%1 = tail call ptr @llvm.stacksave()
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%vla = alloca i32, i64 %0, align 16
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%cmp132 = icmp eq i32 %n, 0
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br i1 %cmp132, label %for.cond.cleanup8, label %for.body.lr.ph
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for.body.lr.ph: ; preds = %if.end
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%sub = add i32 %n, -1
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br label %for.body
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for.cond6.preheader: ; preds = %for.body
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%cmp730 = icmp sgt i32 %n, 0
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br i1 %cmp730, label %for.body9, label %for.cond.cleanup8
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for.body: ; preds = %for.body, %for.body.lr.ph
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%indvars.iv34 = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next35, %for.body ]
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%2 = trunc i64 %indvars.iv34 to i32
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%sub2 = sub i32 %sub, %2
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%idxprom = sext i32 %sub2 to i64
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%arrayidx = getelementptr inbounds i32, ptr %x, i64 %idxprom
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%3 = load i32, ptr %arrayidx, align 4
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%arrayidx4 = getelementptr inbounds i32, ptr %vla, i64 %indvars.iv34
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store i32 %3, ptr %arrayidx4, align 4
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%indvars.iv.next35 = add nuw nsw i64 %indvars.iv34, 1
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%exitcond37 = icmp eq i64 %indvars.iv.next35, %0
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br i1 %exitcond37, label %for.cond6.preheader, label %for.body
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for.cond.cleanup8: ; preds = %for.body9, %if.end, %for.cond6.preheader
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tail call void @llvm.stackrestore(ptr %1)
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br label %return
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for.body9: ; preds = %for.cond6.preheader, %for.body9
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body9 ], [ 0, %for.cond6.preheader ]
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%arrayidx11 = getelementptr inbounds i32, ptr %vla, i64 %indvars.iv
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%4 = load i32, ptr %arrayidx11, align 4
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%add = add nsw i32 %4, 1
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%arrayidx13 = getelementptr inbounds i32, ptr %x, i64 %indvars.iv
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store i32 %add, ptr %arrayidx13, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %0
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br i1 %exitcond, label %for.cond.cleanup8, label %for.body9
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return: ; preds = %entry, %for.cond.cleanup8
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ret void
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}
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; Function Attrs: nounwind
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declare ptr @llvm.stacksave()
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; Function Attrs: nounwind
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declare void @llvm.stackrestore(ptr)
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; Check that llvm.stackrestore() happens before CSRs are popped off the stack
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; CHECK-LABEL: f
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; CHECK: stp x29, x30, [sp, #-16]!
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: mov x29, sp
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; CHECK-NEXT: .cfi_def_cfa w29, 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; VLA allocation
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; CHECK: ubfiz x8, x0, #2, #32
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; CHECK: mov x9, sp
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; CHECK: mov [[SAVE:x[0-9]+]], sp
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; CHECK: add x8, x8, #15
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; CHECK: and [[X1:x[0-9]+]], [[X1]], #0x7fffffff0
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; Saving the SP via llvm.stacksave()
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; CHECK: sub [[X1]], [[X2:x[0-9]+]], [[X1]]
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; The next instruction comes from llvm.stackrestore()
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; CHECK: mov sp, [[SAVE]]
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; Epilogue
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; CHECK-NEXT: mov sp, x29
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; CHECK-NEXT: .cfi_def_cfa wsp, 16
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; CHECK-NEXT: ldp x29, x30, [sp], #16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: .cfi_restore w30
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; CHECK-NEXT: .cfi_restore w29
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; CHECK-NEXT: ret
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