b9e32749d2
As shown in https://alive2.llvm.org/ce/z/PVwcTL we need to clear the nsw flags too when converting a sub to a add if the constant is INT_MIN. Fixes #137254
134 lines
3.8 KiB
LLVM
134 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define i64 @sub1_disguised_constant(i64 %x) {
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; CHECK-SD-LABEL: sub1_disguised_constant:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sub w8, w0, #1
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; CHECK-SD-NEXT: and w8, w0, w8
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; CHECK-SD-NEXT: and x0, x8, #0xffff
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sub1_disguised_constant:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
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; CHECK-GI-NEXT: and x9, x0, #0xffff
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; CHECK-GI-NEXT: add x8, x0, x8
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; CHECK-GI-NEXT: and x0, x9, x8
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; CHECK-GI-NEXT: ret
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%a1 = and i64 %x, 65535
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%a2 = add i64 %x, 65535
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%r = and i64 %a1, %a2
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ret i64 %r
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}
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define i8 @masked_sub_i8(i8 %x) {
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; CHECK-SD-LABEL: masked_sub_i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #5 // =0x5
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; CHECK-SD-NEXT: and w8, w0, w8
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; CHECK-SD-NEXT: eor w0, w8, #0x7
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: masked_sub_i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #5 // =0x5
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; CHECK-GI-NEXT: mov w9, #7 // =0x7
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; CHECK-GI-NEXT: and w8, w0, w8
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; CHECK-GI-NEXT: sub w0, w9, w8
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; CHECK-GI-NEXT: ret
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%a = and i8 %x, 5
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%m = sub i8 7, %a
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ret i8 %m
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}
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; Borrow from the MSB is ok.
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define i8 @masked_sub_high_bit_mask_i8(i8 %x) {
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; CHECK-SD-LABEL: masked_sub_high_bit_mask_i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #-96 // =0xffffffa0
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; CHECK-SD-NEXT: and w8, w0, w8
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; CHECK-SD-NEXT: eor w0, w8, #0x3c
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: masked_sub_high_bit_mask_i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-96 // =0xffffffa0
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; CHECK-GI-NEXT: mov w9, #60 // =0x3c
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; CHECK-GI-NEXT: and w8, w0, w8
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; CHECK-GI-NEXT: sub w0, w9, w8
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; CHECK-GI-NEXT: ret
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%maskx = and i8 %x, 160 ; 0b10100000
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%s = sub i8 60, %maskx ; 0b00111100
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ret i8 %s
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}
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define i8 @not_masked_sub_i8(i8 %x) {
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; CHECK-LABEL: not_masked_sub_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #7 // =0x7
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; CHECK-NEXT: and w9, w0, #0x8
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; CHECK-NEXT: sub w0, w8, w9
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; CHECK-NEXT: ret
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%a = and i8 %x, 8
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%m = sub i8 7, %a
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ret i8 %m
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}
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define i32 @masked_sub_i32(i32 %x) {
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; CHECK-SD-LABEL: masked_sub_i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #9 // =0x9
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; CHECK-SD-NEXT: and w8, w0, w8
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; CHECK-SD-NEXT: eor w0, w8, #0x1f
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: masked_sub_i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #9 // =0x9
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; CHECK-GI-NEXT: mov w9, #31 // =0x1f
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; CHECK-GI-NEXT: and w8, w0, w8
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; CHECK-GI-NEXT: sub w0, w9, w8
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; CHECK-GI-NEXT: ret
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%a = and i32 %x, 9
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%m = sub i32 31, %a
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ret i32 %m
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}
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define <4 x i32> @masked_sub_v4i32(<4 x i32> %x) {
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; CHECK-SD-LABEL: masked_sub_v4i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: movi v1.4s, #42
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; CHECK-SD-NEXT: movi v2.4s, #1, msl #8
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; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: masked_sub_v4i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v1.4s, #42
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; CHECK-GI-NEXT: movi v2.4s, #1, msl #8
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; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-GI-NEXT: sub v0.4s, v2.4s, v0.4s
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; CHECK-GI-NEXT: ret
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%a = and <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
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%m = sub <4 x i32> <i32 511, i32 511, i32 511, i32 511>, %a
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ret <4 x i32> %m
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}
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define i32 @pr137254(i32 %0) {
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; CHECK-LABEL: pr137254:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
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; CHECK-NEXT: add w8, w0, w8
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, gt
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; CHECK-NEXT: ret
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%2 = sub nsw i32 %0, -2147483648
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%3 = icmp sgt i32 %2, 0
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%4 = select i1 %3, i32 1, i32 0
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ret i32 %4
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}
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