15fbdc2b96
Currently, given:
```cpp
svuint8_t foo(uint8_t *x) {
return svld1(svptrue_b8(), x);
}
```
We generate:
```gas
foo:
ptrue p0.b
ld1b { z0.b }, p0/z, [x0]
ret
```
However, on little-endian and with unaligned memory accesses allowed, we
could instead be using LDR as follows:
```gas
foo:
ldr z0, [x0]
ret
```
The second form avoids the predicate dependency.
Likewise for other types and stores.
100 lines
3.2 KiB
LLVM
100 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <vscale x 8 x i8> @extload_icmp_nxv8i8(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: cnot z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%ld = load <vscale x 8 x i8>, ptr %in
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%cmp = icmp eq <vscale x 8 x i8> %ld, zeroinitializer
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%ex = zext <vscale x 8 x i1> %cmp to <vscale x 8 x i8>
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ret <vscale x 8 x i8> %ex
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}
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define <vscale x 16 x i8> @extload_icmp_nxv16i8(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cnot z0.b, p0/m, z0.b
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; CHECK-NEXT: ret
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%ld = load <vscale x 16 x i8>, ptr %in
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%cmp = icmp eq <vscale x 16 x i8> %ld, zeroinitializer
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%ex = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
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ret <vscale x 16 x i8> %ex
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}
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define <vscale x 4 x i16> @extload_icmp_nxv4i16(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: cnot z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%ld = load <vscale x 4 x i16>, ptr %in
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%cmp = icmp eq <vscale x 4 x i16> %ld, zeroinitializer
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%ex = zext <vscale x 4 x i1> %cmp to <vscale x 4 x i16>
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ret <vscale x 4 x i16> %ex
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}
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define <vscale x 8 x i16> @extload_icmp_nxv8i16(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: cnot z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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%ld = load <vscale x 8 x i16>, ptr %in
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%cmp = icmp eq <vscale x 8 x i16> %ld, zeroinitializer
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%ex = zext <vscale x 8 x i1> %cmp to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %ex
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}
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define <vscale x 2 x i32> @extload_icmp_nxv2i32(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
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; CHECK-NEXT: cnot z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%ld = load <vscale x 2 x i32>, ptr %in
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%cmp = icmp eq <vscale x 2 x i32> %ld, zeroinitializer
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%ex = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i32>
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ret <vscale x 2 x i32> %ex
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}
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define <vscale x 4 x i32> @extload_icmp_nxv4i32(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: cnot z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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%ld = load <vscale x 4 x i32>, ptr %in
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%cmp = icmp eq <vscale x 4 x i32> %ld, zeroinitializer
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%ex = zext <vscale x 4 x i1> %cmp to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ex
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}
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define <vscale x 2 x i64> @extload_icmp_nxv2i64(ptr %in) #0 {
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; CHECK-LABEL: extload_icmp_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: cnot z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%ld = load <vscale x 2 x i64>, ptr %in
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%cmp = icmp eq <vscale x 2 x i64> %ld, zeroinitializer
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%ex = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ex
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}
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attributes #0 = { "target-features"="+sve" }
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