db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
273 lines
8.8 KiB
LLVM
273 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE for 64-bit vectors.
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define void @bitcast_v4i16(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <4 x i16>, ptr %a
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%cast = bitcast <4 x i16> %load to <4 x half>
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store volatile <4 x half> %cast, ptr %b
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ret void
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}
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; Don't use SVE for 128-bit vectors.
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define void @bitcast_v8i16(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <8 x i16>, ptr %a
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%cast = bitcast <8 x i16> %load to <8 x half>
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store volatile <8 x half> %cast, ptr %b
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ret void
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}
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define void @bitcast_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl16
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <16 x i16>, ptr %a
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%cast = bitcast <16 x i16> %load to <16 x half>
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store volatile <16 x half> %cast, ptr %b
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ret void
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}
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define void @bitcast_v32i16(ptr %a, ptr %b) #0 {
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; VBITS_GE_256-LABEL: bitcast_v32i16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: bitcast_v32i16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%load = load volatile <32 x i16>, ptr %a
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%cast = bitcast <32 x i16> %load to <32 x half>
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store volatile <32 x half> %cast, ptr %b
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ret void
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}
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define void @bitcast_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {
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; CHECK-LABEL: bitcast_v64i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl64
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <64 x i16>, ptr %a
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%cast = bitcast <64 x i16> %load to <64 x half>
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store volatile <64 x half> %cast, ptr %b
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ret void
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}
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define void @bitcast_v128i16(ptr %a, ptr %b) vscale_range(16,0) #0 {
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; CHECK-LABEL: bitcast_v128i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl128
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <128 x i16>, ptr %a
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%cast = bitcast <128 x i16> %load to <128 x half>
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store volatile <128 x half> %cast, ptr %b
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define void @bitcast_v2i32(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <2 x i32>, ptr %a
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%cast = bitcast <2 x i32> %load to <2 x float>
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store volatile <2 x float> %cast, ptr %b
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ret void
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}
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; Don't use SVE for 128-bit vectors.
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define void @bitcast_v4i32(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <4 x i32>, ptr %a
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%cast = bitcast <4 x i32> %load to <4 x float>
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store volatile <4 x float> %cast, ptr %b
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ret void
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}
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define void @bitcast_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <8 x i32>, ptr %a
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%cast = bitcast <8 x i32> %load to <8 x float>
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store volatile <8 x float> %cast, ptr %b
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ret void
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}
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define void @bitcast_v16i32(ptr %a, ptr %b) #0 {
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; VBITS_GE_256-LABEL: bitcast_v16i32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x1, x8, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: bitcast_v16i32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%load = load volatile <16 x i32>, ptr %a
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%cast = bitcast <16 x i32> %load to <16 x float>
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store volatile <16 x float> %cast, ptr %b
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ret void
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}
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define void @bitcast_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {
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; CHECK-LABEL: bitcast_v32i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <32 x i32>, ptr %a
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%cast = bitcast <32 x i32> %load to <32 x float>
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store volatile <32 x float> %cast, ptr %b
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ret void
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}
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define void @bitcast_v64i32(ptr %a, ptr %b) vscale_range(16,0) #0 {
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; CHECK-LABEL: bitcast_v64i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl64
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <64 x i32>, ptr %a
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%cast = bitcast <64 x i32> %load to <64 x float>
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store volatile <64 x float> %cast, ptr %b
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define void @bitcast_v1i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: str d0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <1 x i64>, ptr %a
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%cast = bitcast <1 x i64> %load to <1 x double>
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store volatile <1 x double> %cast, ptr %b
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ret void
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}
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; Don't use SVE for 128-bit vectors.
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define void @bitcast_v2i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <2 x i64>, ptr %a
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%cast = bitcast <2 x i64> %load to <2 x double>
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store volatile <2 x double> %cast, ptr %b
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ret void
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}
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define void @bitcast_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
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; CHECK-LABEL: bitcast_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <4 x i64>, ptr %a
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%cast = bitcast <4 x i64> %load to <4 x double>
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store volatile <4 x double> %cast, ptr %b
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ret void
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}
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define void @bitcast_v8i64(ptr %a, ptr %b) #0 {
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; VBITS_GE_256-LABEL: bitcast_v8i64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x1, x8, lsl #3]
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; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: bitcast_v8i64:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%load = load volatile <8 x i64>, ptr %a
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%cast = bitcast <8 x i64> %load to <8 x double>
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store volatile <8 x double> %cast, ptr %b
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ret void
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}
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define void @bitcast_v16i64(ptr %a, ptr %b) vscale_range(8,0) #0 {
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; CHECK-LABEL: bitcast_v16i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl16
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <16 x i64>, ptr %a
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%cast = bitcast <16 x i64> %load to <16 x double>
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store volatile <16 x double> %cast, ptr %b
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ret void
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}
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define void @bitcast_v32i64(ptr %a, ptr %b) vscale_range(16,0) #0 {
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; CHECK-LABEL: bitcast_v32i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl32
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%load = load volatile <32 x i64>, ptr %a
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%cast = bitcast <32 x i64> %load to <32 x double>
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store volatile <32 x double> %cast, ptr %b
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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