61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
191 lines
6.0 KiB
LLVM
191 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; Unpredicated dup instruction (which is an alias for mov):
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; * register + register,
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; * register + immediate
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;
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define <vscale x 16 x i8> @dup_i8(i8 %b) {
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; CHECK-LABEL: dup_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.b, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 16 x i8> @dup_imm_i8() {
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; CHECK-LABEL: dup_imm_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.b, #16 // =0x10
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 16)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @dup_i16(i16 %b) {
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; CHECK-LABEL: dup_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.h, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 8 x i16> @dup_imm_i16(i16 %b) {
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; CHECK-LABEL: dup_imm_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.h, #16 // =0x10
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 16)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @dup_i32(i32 %b) {
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; CHECK-LABEL: dup_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.s, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 4 x i32> @dup_imm_i32(i32 %b) {
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; CHECK-LABEL: dup_imm_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.s, #16 // =0x10
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 16)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @dup_i64(i64 %b) {
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; CHECK-LABEL: dup_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.d, x0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %b)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 2 x i64> @dup_imm_i64(i64 %b) {
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; CHECK-LABEL: dup_imm_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z0.d, #16 // =0x10
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 16)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x half> @dup_f16(half %b) {
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; CHECK-LABEL: dup_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
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; CHECK-NEXT: mov z0.h, h0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %b)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 8 x bfloat> @dup_bf16(bfloat %b) #0 {
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; CHECK-LABEL: dup_bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
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; CHECK-NEXT: mov z0.h, h0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %b)
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ret <vscale x 8 x bfloat> %out
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}
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define <vscale x 8 x half> @dup_imm_f16(half %b) {
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; CHECK-LABEL: dup_imm_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov z0.h, #16.00000000
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half 16.)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 4 x float> @dup_f32(float %b) {
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; CHECK-LABEL: dup_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0
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; CHECK-NEXT: mov z0.s, s0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %b)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 4 x float> @dup_imm_f32(float %b) {
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; CHECK-LABEL: dup_imm_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov z0.s, #16.00000000
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float 16.)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 2 x double> @dup_f64(double %b) {
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; CHECK-LABEL: dup_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z0.d, d0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %b)
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ret <vscale x 2 x double> %out
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}
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define <vscale x 2 x double> @dup_imm_f64(double %b) {
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; CHECK-LABEL: dup_imm_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov z0.d, #16.00000000
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double 16.)
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ret <vscale x 2 x double> %out
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}
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define <vscale x 2 x float> @dup_fmov_imm_f32_2() {
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; CHECK-LABEL: dup_fmov_imm_f32_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1109917696
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; CHECK-NEXT: mov z0.s, w8
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; CHECK-NEXT: ret
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%out = tail call <vscale x 2 x float> @llvm.aarch64.sve.dup.x.nxv2f32(float 4.200000e+01)
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ret <vscale x 2 x float> %out
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}
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define <vscale x 4 x float> @dup_fmov_imm_f32_4() {
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; CHECK-LABEL: dup_fmov_imm_f32_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1109917696
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; CHECK-NEXT: mov z0.s, w8
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; CHECK-NEXT: ret
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%out = tail call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float 4.200000e+01)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 2 x double> @dup_fmov_imm_f64_2() {
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; CHECK-LABEL: dup_fmov_imm_f64_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #4631107791820423168
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; CHECK-NEXT: mov z0.d, x8
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; CHECK-NEXT: ret
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%out = tail call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double 4.200000e+01)
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ret <vscale x 2 x double> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8( i8)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64)
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declare <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat)
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declare <vscale x 2 x float> @llvm.aarch64.sve.dup.x.nxv2f32(float)
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declare <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float)
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declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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