34d88cf6cf
This now allows folding an AND of a anyext masked_load to a zext_masked_load even if the masked load has multiple users. Doing is eliminates some redundant ANDs/MOVs for certain AArch64 SVE code. I'm not sure if there's any cases where doing this could negatively the other users of the masked_load. Looking at other optimizations of masked loads, most don't apply if the load is used more than once, so it doesn't look like this would interfere. Reviewed By: c-rhodes Differential Revision: https://reviews.llvm.org/D137844
31 lines
1.9 KiB
LLVM
31 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
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define void @sve_load_compare_store(ptr noalias nocapture noundef readonly %a, ptr noalias nocapture noundef %b) {
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; CHECK-LABEL: sve_load_compare_store:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, #0
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; CHECK-NEXT: st1b { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
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%2 = tail call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr %a, i32 1, <vscale x 4 x i1> %1, <vscale x 4 x i16> zeroinitializer)
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%3 = zext <vscale x 4 x i16> %2 to <vscale x 4 x i32>
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%4 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 4 x i32> zeroinitializer)
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%5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
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%6 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>
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tail call void @llvm.masked.store.nxv4i8.p0(<vscale x 4 x i8> %6, ptr %b, i32 1, <vscale x 4 x i1> %4)
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ret void
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
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declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i16>)
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declare void @llvm.masked.store.nxv4i8.p0(<vscale x 4 x i8>, ptr, i32 immarg, <vscale x 4 x i1>)
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