9828745661
The patch adds patterns to select the EXT_ZZI_CONSTRUCTIVE pseudo instead of the EXT_ZZI destructive instruction for vector_splice. This only works when the two inputs to vector_splice are identical. Given that registers aren't tied anymore, this gives the register allocator more freedom and a lot of MOVs get replaced with MOVPRFX. In some cases however, we could have just chosen the same input and output register, but regalloc preferred not to. This means we end up with some test cases now having more instructions: there is now a MOVPRFX while no MOV was previously needed.
3413 lines
121 KiB
LLVM
3413 lines
121 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
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; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
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target triple = "aarch64-unknown-linux-gnu"
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;
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; FCVTZU H -> H
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;
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define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) {
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; CHECK-LABEL: fcvtzu_v4f16_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl4
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i16:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #6]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #4]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #14]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #12]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #10]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #8]
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; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
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; NONEON-NOSVE-NEXT: add sp, sp, #16
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; NONEON-NOSVE-NEXT: ret
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%res = fptoui <4 x half> %op1 to <4 x i16>
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ret <4 x i16> %res
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}
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define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) {
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; CHECK-LABEL: fcvtzu_v8f16_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i16:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: ldr q0, [x0]
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; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #30]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #28]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #26]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #6]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #24]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #4]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #22]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #20]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #18]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #16]
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; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
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; NONEON-NOSVE-NEXT: str q0, [x1]
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; NONEON-NOSVE-NEXT: add sp, sp, #32
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; NONEON-NOSVE-NEXT: ret
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%op1 = load <8 x half>, ptr %a
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%res = fptoui <8 x half> %op1 to <8 x i16>
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store <8 x i16> %res, ptr %b
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ret void
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}
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define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) {
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; CHECK-LABEL: fcvtzu_v16f16_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: ptrue p0.h, vl8
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; CHECK-NEXT: fcvtzu z0.h, p0/m, z0.h
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; CHECK-NEXT: fcvtzu z1.h, p0/m, z1.h
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i16:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
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; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-64]!
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #62]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #60]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #58]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #56]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #54]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #52]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #50]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #48]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #46]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #44]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #42]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #6]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #40]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #4]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #38]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #36]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #34]
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; NONEON-NOSVE-NEXT: fcvtzs w8, s0
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; NONEON-NOSVE-NEXT: strh w8, [sp, #32]
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; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
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; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
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; NONEON-NOSVE-NEXT: add sp, sp, #64
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; NONEON-NOSVE-NEXT: ret
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%op1 = load <16 x half>, ptr %a
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%res = fptoui <16 x half> %op1 to <16 x i16>
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store <16 x i16> %res, ptr %b
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ret void
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}
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;
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; FCVTZU H -> S
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;
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define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) {
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; CHECK-LABEL: fcvtzu_v2f16_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fcvtzu_v2f16_v2i32:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
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; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
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; NONEON-NOSVE-NEXT: add sp, sp, #16
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; NONEON-NOSVE-NEXT: ret
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%res = fptoui <2 x half> %op1 to <2 x i32>
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ret <2 x i32> %res
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}
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define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) {
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; CHECK-LABEL: fcvtzu_v4f16_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i32:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: sub sp, sp, #32
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
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; NONEON-NOSVE-NEXT: str d0, [sp, #8]
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16]
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; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
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; NONEON-NOSVE-NEXT: add sp, sp, #32
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; NONEON-NOSVE-NEXT: ret
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%res = fptoui <4 x half> %op1 to <4 x i32>
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ret <4 x i32> %res
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}
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define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) {
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; CHECK-LABEL: fcvtzu_v8f16_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ptrue p0.s, vl4
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; CHECK-NEXT: movprfx z1, z0
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; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: uunpklo z1.s, z1.h
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; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
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; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.h
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i32:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: ldr q0, [x0]
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; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
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; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
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; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #56]
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
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; NONEON-NOSVE-NEXT: fcvtzu w9, s0
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; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]
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; NONEON-NOSVE-NEXT: fcvt s0, h0
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; NONEON-NOSVE-NEXT: fcvtzu w8, s0
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #32]
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; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
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; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
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; NONEON-NOSVE-NEXT: add sp, sp, #64
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; NONEON-NOSVE-NEXT: ret
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%op1 = load <8 x half>, ptr %a
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%res = fptoui <8 x half> %op1 to <8 x i32>
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store <8 x i32> %res, ptr %b
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|
ret void
|
|
}
|
|
|
|
define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v16f16_v16i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: movprfx z2, z0
|
|
; CHECK-NEXT: ext z2.b, z2.b, z0.b, #8
|
|
; CHECK-NEXT: movprfx z3, z1
|
|
; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzu z2.s, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzu z3.s, p0/m, z3.h
|
|
; CHECK-NEXT: stp q1, q3, [x1]
|
|
; CHECK-NEXT: stp q0, q2, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #120]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #104]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp q2, q3, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #128
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%res = fptoui <16 x half> %op1 to <16 x i32>
|
|
store <16 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU H -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v1f16_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v1f16_v1i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <1 x half> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f16_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f16_v2i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x half> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v4f16_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: mov z2.h, z0.h[2]
|
|
; CHECK-NEXT: mov z3.h, z0.h[1]
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.h
|
|
; CHECK-NEXT: zip1 z1.d, z2.d, z1.d
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48
|
|
; NONEON-NOSVE-NEXT: ldr d0, [x0]
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x half>, ptr %a
|
|
%res = fptoui <4 x half> %op1 to <4 x i64>
|
|
store <4 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v8f16_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: mov z2.h, z0.h[3]
|
|
; CHECK-NEXT: mov z3.h, z0.h[2]
|
|
; CHECK-NEXT: mov z4.h, z0.h[1]
|
|
; CHECK-NEXT: movprfx z1, z0
|
|
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.h
|
|
; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.h
|
|
; CHECK-NEXT: mov z5.h, z1.h[3]
|
|
; CHECK-NEXT: mov z6.h, z1.h[2]
|
|
; CHECK-NEXT: mov z7.h, z1.h[1]
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.h
|
|
; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.h
|
|
; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.h
|
|
; CHECK-NEXT: zip1 z2.d, z3.d, z2.d
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z4.d
|
|
; CHECK-NEXT: zip1 z3.d, z6.d, z5.d
|
|
; CHECK-NEXT: zip1 z1.d, z1.d, z7.d
|
|
; CHECK-NEXT: stp q0, q2, [x1]
|
|
; CHECK-NEXT: stp q1, q3, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldr q0, [x0]
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-96]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q2, q3, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x half>, ptr %a
|
|
%res = fptoui <8 x half> %op1 to <8 x i64>
|
|
store <8 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v16f16_v16i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: mov z2.h, z1.h[1]
|
|
; CHECK-NEXT: mov z3.h, z0.h[3]
|
|
; CHECK-NEXT: mov z4.h, z0.h[2]
|
|
; CHECK-NEXT: movprfx z5, z1
|
|
; CHECK-NEXT: ext z5.b, z5.b, z1.b, #8
|
|
; CHECK-NEXT: movprfx z7, z1
|
|
; CHECK-NEXT: fcvtzu z7.d, p0/m, z1.h
|
|
; CHECK-NEXT: mov z16.h, z1.h[3]
|
|
; CHECK-NEXT: mov z1.h, z1.h[2]
|
|
; CHECK-NEXT: mov z17.h, z0.h[1]
|
|
; CHECK-NEXT: movprfx z6, z0
|
|
; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8
|
|
; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.h
|
|
; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.h
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzu z16.d, p0/m, z16.h
|
|
; CHECK-NEXT: mov z18.h, z5.h[3]
|
|
; CHECK-NEXT: fcvtzu z17.d, p0/m, z17.h
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: mov z19.h, z6.h[3]
|
|
; CHECK-NEXT: mov z20.h, z6.h[2]
|
|
; CHECK-NEXT: mov z21.h, z6.h[1]
|
|
; CHECK-NEXT: fcvtzu z6.d, p0/m, z6.h
|
|
; CHECK-NEXT: zip1 z2.d, z7.d, z2.d
|
|
; CHECK-NEXT: mov z7.h, z5.h[2]
|
|
; CHECK-NEXT: zip1 z3.d, z4.d, z3.d
|
|
; CHECK-NEXT: mov z4.h, z5.h[1]
|
|
; CHECK-NEXT: fcvtzu z19.d, p0/m, z19.h
|
|
; CHECK-NEXT: fcvtzu z5.d, p0/m, z5.h
|
|
; CHECK-NEXT: fcvtzu z20.d, p0/m, z20.h
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z17.d
|
|
; CHECK-NEXT: movprfx z17, z21
|
|
; CHECK-NEXT: fcvtzu z17.d, p0/m, z21.h
|
|
; CHECK-NEXT: zip1 z1.d, z1.d, z16.d
|
|
; CHECK-NEXT: movprfx z16, z18
|
|
; CHECK-NEXT: fcvtzu z16.d, p0/m, z18.h
|
|
; CHECK-NEXT: fcvtzu z7.d, p0/m, z7.h
|
|
; CHECK-NEXT: fcvtzu z4.d, p0/m, z4.h
|
|
; CHECK-NEXT: stp q0, q3, [x1, #64]
|
|
; CHECK-NEXT: zip1 z0.d, z20.d, z19.d
|
|
; CHECK-NEXT: zip1 z3.d, z6.d, z17.d
|
|
; CHECK-NEXT: stp q2, q1, [x1]
|
|
; CHECK-NEXT: zip1 z1.d, z7.d, z16.d
|
|
; CHECK-NEXT: zip1 z2.d, z5.d, z4.d
|
|
; CHECK-NEXT: stp q3, q0, [x1, #96]
|
|
; CHECK-NEXT: stp q2, q1, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #192
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 192
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [sp]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q3, q4, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #176]
|
|
; NONEON-NOSVE-NEXT: ldp q6, q7, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #144]
|
|
; NONEON-NOSVE-NEXT: ldp q5, q2, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q3, q4, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: stp q6, q7, [x1, #64]
|
|
; NONEON-NOSVE-NEXT: stp q5, q2, [x1, #96]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #192
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%res = fptoui <16 x half> %op1 to <16 x i64>
|
|
store <16 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU S -> H
|
|
;
|
|
|
|
define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f32_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x float> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v4f32_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <4 x float> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) {
|
|
; CHECK-LABEL: fcvtzu_v8f32_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x float>, ptr %a
|
|
%res = fptoui <8 x float> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v16f32_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ldp q2, q3, [x0]
|
|
; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzu z3.s, p0/m, z3.s
|
|
; CHECK-NEXT: fcvtzu z2.s, p0/m, z2.s
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
|
|
; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
|
|
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
|
|
; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h
|
|
; CHECK-NEXT: stp q2, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v16f32_v16i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: str q1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp q3, q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: str q2, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #78]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #76]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #74]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #70]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #68]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #66]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #94]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #92]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #90]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #86]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #84]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #82]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x float>, ptr %a
|
|
%res = fptoui <16 x float> %op1 to <16 x i16>
|
|
store <16 x i16> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU S -> S
|
|
;
|
|
|
|
define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f32_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x float> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v4f32_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <4 x float> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v8f32_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x float>, ptr %a
|
|
%res = fptoui <8 x float> %op1 to <8 x i32>
|
|
store <8 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU S -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v1f32_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v1f32_v1i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr s0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: fmov d0, x8
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <1 x float> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f32_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x float> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v4f32_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: movprfx z1, z0
|
|
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: uunpklo z1.d, z1.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldr q0, [x0]
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x float>, ptr %a
|
|
%res = fptoui <4 x float> %op1 to <4 x i64>
|
|
store <4 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v8f32_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: movprfx z2, z0
|
|
; CHECK-NEXT: ext z2.b, z2.b, z0.b, #8
|
|
; CHECK-NEXT: movprfx z3, z1
|
|
; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: uunpklo z1.d, z1.s
|
|
; CHECK-NEXT: uunpklo z2.d, z2.s
|
|
; CHECK-NEXT: uunpklo z3.d, z3.s
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.s
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.s
|
|
; CHECK-NEXT: stp q1, q3, [x1]
|
|
; CHECK-NEXT: stp q0, q2, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp q2, q3, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #128
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x float>, ptr %a
|
|
%res = fptoui <8 x float> %op1 to <8 x i64>
|
|
store <8 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU D -> H
|
|
;
|
|
|
|
define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v1f64_v1i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: fcvtzs w8, d0
|
|
; CHECK-NEXT: mov z0.h, w8
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <1 x double> %op1 to <1 x i16>
|
|
ret <1 x i16> %res
|
|
}
|
|
|
|
define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f64_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x double> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) {
|
|
; CHECK-LABEL: fcvtzu_v4f64_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: mov z2.s, z1.s[1]
|
|
; CHECK-NEXT: mov z3.s, z0.s[1]
|
|
; CHECK-NEXT: zip1 z1.h, z1.h, z2.h
|
|
; CHECK-NEXT: zip1 z0.h, z0.h, z3.h
|
|
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-80]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #78]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #76]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #74]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #80
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x double>, ptr %a
|
|
%res = fptoui <4 x double> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) {
|
|
; CHECK-LABEL: fcvtzu_v8f64_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x0]
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: mov z4.s, z0.s[1]
|
|
; CHECK-NEXT: mov z5.s, z1.s[1]
|
|
; CHECK-NEXT: mov z6.s, z3.s[1]
|
|
; CHECK-NEXT: mov z7.s, z2.s[1]
|
|
; CHECK-NEXT: zip1 z0.h, z0.h, z4.h
|
|
; CHECK-NEXT: zip1 z1.h, z1.h, z5.h
|
|
; CHECK-NEXT: zip1 z3.h, z3.h, z6.h
|
|
; CHECK-NEXT: zip1 z2.h, z2.h, z7.h
|
|
; CHECK-NEXT: zip1 z0.s, z1.s, z0.s
|
|
; CHECK-NEXT: zip1 z1.s, z2.s, z3.s
|
|
; CHECK-NEXT: zip1 z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v8f64_v8i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #144
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 144
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0]
|
|
; NONEON-NOSVE-NEXT: str q1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: str q2, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d2, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldr d1, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #104]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #104]
|
|
; NONEON-NOSVE-NEXT: str d2, [sp, #120]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #142]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #140]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #120]
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #138]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #136]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #134]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #132]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #130]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #144
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x double>, ptr %a
|
|
%res = fptoui <8 x double> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v16f64_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #96]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x0, #32]
|
|
; CHECK-NEXT: ldp q4, q5, [x0, #64]
|
|
; CHECK-NEXT: ldp q6, q7, [x0]
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
|
|
; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
|
|
; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s
|
|
; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s
|
|
; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s
|
|
; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s
|
|
; CHECK-NEXT: mov z17.s, z1.s[1]
|
|
; CHECK-NEXT: mov z16.s, z3.s[1]
|
|
; CHECK-NEXT: mov z18.s, z0.s[1]
|
|
; CHECK-NEXT: mov z21.s, z2.s[1]
|
|
; CHECK-NEXT: mov z19.s, z5.s[1]
|
|
; CHECK-NEXT: mov z20.s, z4.s[1]
|
|
; CHECK-NEXT: mov z22.s, z7.s[1]
|
|
; CHECK-NEXT: mov z23.s, z6.s[1]
|
|
; CHECK-NEXT: zip1 z1.h, z1.h, z17.h
|
|
; CHECK-NEXT: zip1 z3.h, z3.h, z16.h
|
|
; CHECK-NEXT: zip1 z0.h, z0.h, z18.h
|
|
; CHECK-NEXT: zip1 z2.h, z2.h, z21.h
|
|
; CHECK-NEXT: zip1 z5.h, z5.h, z19.h
|
|
; CHECK-NEXT: zip1 z4.h, z4.h, z20.h
|
|
; CHECK-NEXT: zip1 z7.h, z7.h, z22.h
|
|
; CHECK-NEXT: zip1 z6.h, z6.h, z23.h
|
|
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: zip1 z2.s, z2.s, z3.s
|
|
; CHECK-NEXT: zip1 z1.s, z4.s, z5.s
|
|
; CHECK-NEXT: zip1 z3.s, z6.s, z7.s
|
|
; CHECK-NEXT: zip1 z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: zip1 z1.d, z3.d, z2.d
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v16f64_v16i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #304
|
|
; NONEON-NOSVE-NEXT: str x29, [sp, #288] // 8-byte Folded Spill
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 304
|
|
; NONEON-NOSVE-NEXT: .cfi_offset w29, -16
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: ldr x29, [sp, #288] // 8-byte Folded Reload
|
|
; NONEON-NOSVE-NEXT: ldp q6, q7, [x0]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #64]
|
|
; NONEON-NOSVE-NEXT: ldp q4, q5, [x0, #96]
|
|
; NONEON-NOSVE-NEXT: stp q1, q7, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q6, q4, [sp]
|
|
; NONEON-NOSVE-NEXT: stp q5, q3, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #168]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #184]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #176]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #136]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #152]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #144]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d2, [sp, #176]
|
|
; NONEON-NOSVE-NEXT: ldr d1, [sp, #168]
|
|
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #232]
|
|
; NONEON-NOSVE-NEXT: ldr d1, [sp, #136]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #192]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #232]
|
|
; NONEON-NOSVE-NEXT: str d2, [sp, #248]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d2, [sp, #144]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #270]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #268]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #248]
|
|
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #200]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #266]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #264]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #240]
|
|
; NONEON-NOSVE-NEXT: stp d2, d0, [sp, #216]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #192]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #262]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #260]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #200]
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #296]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #258]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #256]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #216]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #286]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #284]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #208]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #282]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #280]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #224]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #276]
|
|
; NONEON-NOSVE-NEXT: ldr w8, [sp, #300]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #278]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #274]
|
|
; NONEON-NOSVE-NEXT: ldr w8, [sp, #296]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #272]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #256]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #304
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x double>, ptr %a
|
|
%res = fptoui <16 x double> %op1 to <16 x i16>
|
|
store <16 x i16> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU D -> S
|
|
;
|
|
|
|
define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v1f64_v1i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: str w8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <1 x double> %op1 to <1 x i32>
|
|
ret <1 x i32> %res
|
|
}
|
|
|
|
define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f64_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x double> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) {
|
|
; CHECK-LABEL: fcvtzu_v4f64_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x double>, ptr %a
|
|
%res = fptoui <4 x double> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v8f64_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x0]
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzu z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fcvtzu z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
|
|
; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s
|
|
; CHECK-NEXT: stp q2, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v8f64_v8i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: str q1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp q3, q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: str q2, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzu w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x double>, ptr %a
|
|
%res = fptoui <8 x double> %op1 to <8 x i32>
|
|
store <8 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZU D -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v1f64_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl1
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, d0
|
|
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <1 x double> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzu_v2f64_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, d0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptoui <2 x double> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzu_v4f64_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzu x9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzu x8, d0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x double>, ptr %a
|
|
%res = fptoui <4 x double> %op1 to <4 x i64>
|
|
store <4 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS H -> H
|
|
;
|
|
|
|
define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v4f16_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #6]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #4]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #14]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #12]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <4 x half> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v8f16_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: str q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldr q0, [x0]
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #6]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #4]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #22]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #20]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #18]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: str q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x half>, ptr %a
|
|
%res = fptosi <8 x half> %op1 to <8 x i16>
|
|
store <8 x i16> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v16f16_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: fcvtzs z0.h, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.h, p0/m, z1.h
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #62]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #60]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #58]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #54]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #52]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #50]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #6]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #4]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%res = fptosi <16 x half> %op1 to <16 x i16>
|
|
store <16 x i16> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS H -> S
|
|
;
|
|
|
|
define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f16_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f16_v2i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #2]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x half> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v4f16_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <4 x half> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v8f16_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: movprfx z1, z0
|
|
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.h
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldr q0, [x0]
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x half>, ptr %a
|
|
%res = fptosi <8 x half> %op1 to <8 x i32>
|
|
store <8 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v16f16_v16i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: movprfx z2, z0
|
|
; CHECK-NEXT: ext z2.b, z2.b, z0.b, #8
|
|
; CHECK-NEXT: movprfx z3, z1
|
|
; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzs z2.s, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzs z3.s, p0/m, z3.h
|
|
; CHECK-NEXT: stp q1, q3, [x1]
|
|
; CHECK-NEXT: stp q0, q2, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #120]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #104]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp q2, q3, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #128
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%res = fptosi <16 x half> %op1 to <16 x i32>
|
|
store <16 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS H -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v1f16_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v1f16_v1i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <1 x half> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
; v2f16 is not legal for NEON, so use SVE
|
|
define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f16_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: mov z1.h, z0.h[1]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z1.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f16_v2i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x half> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v4f16_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: mov z1.h, z0.h[3]
|
|
; CHECK-NEXT: mov z2.h, z0.h[2]
|
|
; CHECK-NEXT: mov z3.h, z0.h[1]
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
|
|
; CHECK-NEXT: zip1 z1.d, z2.d, z1.d
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z3.d
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48
|
|
; NONEON-NOSVE-NEXT: ldr d0, [x0]
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #10]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #14]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #12]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x half>, ptr %a
|
|
%res = fptosi <4 x half> %op1 to <4 x i64>
|
|
store <4 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v8f16_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: mov z2.h, z0.h[3]
|
|
; CHECK-NEXT: mov z3.h, z0.h[2]
|
|
; CHECK-NEXT: mov z4.h, z0.h[1]
|
|
; CHECK-NEXT: movprfx z1, z0
|
|
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
|
|
; CHECK-NEXT: mov z5.h, z1.h[3]
|
|
; CHECK-NEXT: mov z6.h, z1.h[2]
|
|
; CHECK-NEXT: mov z7.h, z1.h[1]
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
|
|
; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
|
|
; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
|
|
; CHECK-NEXT: zip1 z2.d, z3.d, z2.d
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z4.d
|
|
; CHECK-NEXT: zip1 z3.d, z6.d, z5.d
|
|
; CHECK-NEXT: zip1 z1.d, z1.d, z7.d
|
|
; CHECK-NEXT: stp q0, q2, [x1]
|
|
; CHECK-NEXT: stp q1, q3, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldr q0, [x0]
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-96]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #18]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #22]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #20]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q2, q3, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x half>, ptr %a
|
|
%res = fptosi <8 x half> %op1 to <8 x i64>
|
|
store <8 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v16f16_v16i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d
|
|
; CHECK-NEXT: mov z2.h, z1.h[1]
|
|
; CHECK-NEXT: mov z3.h, z0.h[3]
|
|
; CHECK-NEXT: mov z4.h, z0.h[2]
|
|
; CHECK-NEXT: movprfx z5, z1
|
|
; CHECK-NEXT: ext z5.b, z5.b, z1.b, #8
|
|
; CHECK-NEXT: movprfx z7, z1
|
|
; CHECK-NEXT: fcvtzs z7.d, p0/m, z1.h
|
|
; CHECK-NEXT: mov z16.h, z1.h[3]
|
|
; CHECK-NEXT: mov z1.h, z1.h[2]
|
|
; CHECK-NEXT: mov z17.h, z0.h[1]
|
|
; CHECK-NEXT: movprfx z6, z0
|
|
; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.h
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.h
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.h
|
|
; CHECK-NEXT: fcvtzs z16.d, p0/m, z16.h
|
|
; CHECK-NEXT: mov z18.h, z5.h[3]
|
|
; CHECK-NEXT: fcvtzs z17.d, p0/m, z17.h
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.h
|
|
; CHECK-NEXT: mov z19.h, z6.h[3]
|
|
; CHECK-NEXT: mov z20.h, z6.h[2]
|
|
; CHECK-NEXT: mov z21.h, z6.h[1]
|
|
; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.h
|
|
; CHECK-NEXT: zip1 z2.d, z7.d, z2.d
|
|
; CHECK-NEXT: mov z7.h, z5.h[2]
|
|
; CHECK-NEXT: zip1 z3.d, z4.d, z3.d
|
|
; CHECK-NEXT: mov z4.h, z5.h[1]
|
|
; CHECK-NEXT: fcvtzs z19.d, p0/m, z19.h
|
|
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.h
|
|
; CHECK-NEXT: fcvtzs z20.d, p0/m, z20.h
|
|
; CHECK-NEXT: zip1 z0.d, z0.d, z17.d
|
|
; CHECK-NEXT: movprfx z17, z21
|
|
; CHECK-NEXT: fcvtzs z17.d, p0/m, z21.h
|
|
; CHECK-NEXT: zip1 z1.d, z1.d, z16.d
|
|
; CHECK-NEXT: movprfx z16, z18
|
|
; CHECK-NEXT: fcvtzs z16.d, p0/m, z18.h
|
|
; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.h
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.h
|
|
; CHECK-NEXT: stp q0, q3, [x1, #64]
|
|
; CHECK-NEXT: zip1 z0.d, z20.d, z19.d
|
|
; CHECK-NEXT: zip1 z3.d, z6.d, z17.d
|
|
; CHECK-NEXT: stp q2, q1, [x1]
|
|
; CHECK-NEXT: zip1 z1.d, z7.d, z16.d
|
|
; CHECK-NEXT: zip1 z2.d, z5.d, z4.d
|
|
; CHECK-NEXT: stp q3, q0, [x1, #96]
|
|
; CHECK-NEXT: stp q2, q1, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #192
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 192
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [sp]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #58]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q3, q4, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #62]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #60]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #50]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #176]
|
|
; NONEON-NOSVE-NEXT: ldp q6, q7, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #54]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s0
|
|
; NONEON-NOSVE-NEXT: ldr h0, [sp, #52]
|
|
; NONEON-NOSVE-NEXT: fcvt s0, h0
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #144]
|
|
; NONEON-NOSVE-NEXT: ldp q5, q2, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q3, q4, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: stp q6, q7, [x1, #64]
|
|
; NONEON-NOSVE-NEXT: stp q5, q2, [x1, #96]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #192
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%res = fptosi <16 x half> %op1 to <16 x i64>
|
|
store <16 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS S -> H
|
|
;
|
|
|
|
define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f32_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x float> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v4f32_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #30]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #28]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #26]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <4 x float> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) {
|
|
; CHECK-LABEL: fcvtzs_v8f32_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #46]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #44]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #42]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #38]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #36]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #34]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x float>, ptr %a
|
|
%res = fptosi <8 x float> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v16f32_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: ldp q2, q3, [x0]
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzs z3.s, p0/m, z3.s
|
|
; CHECK-NEXT: fcvtzs z2.s, p0/m, z2.s
|
|
; CHECK-NEXT: ptrue p0.h, vl4
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
|
|
; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
|
|
; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h
|
|
; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h
|
|
; CHECK-NEXT: stp q2, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v16f32_v16i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: str q1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp q3, q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: str q2, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #78]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #76]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #74]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #70]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #68]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #66]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #94]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #92]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #90]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #86]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #84]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s1
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #82]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x float>, ptr %a
|
|
%res = fptosi <16 x float> %op1 to <16 x i16>
|
|
store <16 x i16> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS S -> S
|
|
;
|
|
|
|
define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f32_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x float> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v4f32_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <4 x float> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v8f32_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.s, vl4
|
|
; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, s0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x float>, ptr %a
|
|
%res = fptosi <8 x float> %op1 to <8 x i32>
|
|
store <8 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS S -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v1f32_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v1f32_v1i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr s0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: fmov d0, x8
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <1 x float> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f32_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x float> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v4f32_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: movprfx z1, z0
|
|
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: uunpklo z1.d, z1.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldr q0, [x0]
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x float>, ptr %a
|
|
%res = fptosi <4 x float> %op1 to <4 x i64>
|
|
store <4 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v8f32_v8i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: movprfx z2, z0
|
|
; CHECK-NEXT: ext z2.b, z2.b, z0.b, #8
|
|
; CHECK-NEXT: movprfx z3, z1
|
|
; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8
|
|
; CHECK-NEXT: uunpklo z0.d, z0.s
|
|
; CHECK-NEXT: uunpklo z1.d, z1.s
|
|
; CHECK-NEXT: uunpklo z2.d, z2.s
|
|
; CHECK-NEXT: uunpklo z3.d, z3.s
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.s
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.s
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.s
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.s
|
|
; CHECK-NEXT: stp q1, q3, [x1]
|
|
; CHECK-NEXT: stp q0, q2, [x1, #32]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: ldp s0, s1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, s1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, s0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp q2, q3, [x1]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #128
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x float>, ptr %a
|
|
%res = fptosi <8 x float> %op1 to <8 x i64>
|
|
store <8 x i64> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
|
|
;
|
|
; FCVTZS D -> H
|
|
;
|
|
|
|
; v1f64 is perfered to be widened to v4f64, so use SVE
|
|
define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v1f64_v1i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: fcvtzs w8, d0
|
|
; CHECK-NEXT: mov z0.h, w8
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <1 x double> %op1 to <1 x i16>
|
|
ret <1 x i16> %res
|
|
}
|
|
|
|
define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f64_v2i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x double> %op1 to <2 x i16>
|
|
ret <2 x i16> %res
|
|
}
|
|
|
|
define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) {
|
|
; CHECK-LABEL: fcvtzs_v4f64_v4i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: mov z2.s, z1.s[1]
|
|
; CHECK-NEXT: mov z3.s, z0.s[1]
|
|
; CHECK-NEXT: zip1 z1.h, z1.h, z2.h
|
|
; CHECK-NEXT: zip1 z0.h, z0.h, z3.h
|
|
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-80]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #78]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #76]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #56]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #74]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #80
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x double>, ptr %a
|
|
%res = fptosi <4 x double> %op1 to <4 x i16>
|
|
ret <4 x i16> %res
|
|
}
|
|
|
|
define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) {
|
|
; CHECK-LABEL: fcvtzs_v8f64_v8i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q1, q0, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x0]
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: mov z4.s, z0.s[1]
|
|
; CHECK-NEXT: mov z5.s, z1.s[1]
|
|
; CHECK-NEXT: mov z6.s, z3.s[1]
|
|
; CHECK-NEXT: mov z7.s, z2.s[1]
|
|
; CHECK-NEXT: zip1 z0.h, z0.h, z4.h
|
|
; CHECK-NEXT: zip1 z1.h, z1.h, z5.h
|
|
; CHECK-NEXT: zip1 z3.h, z3.h, z6.h
|
|
; CHECK-NEXT: zip1 z2.h, z2.h, z7.h
|
|
; CHECK-NEXT: zip1 z0.s, z1.s, z0.s
|
|
; CHECK-NEXT: zip1 z1.s, z2.s, z3.s
|
|
; CHECK-NEXT: zip1 z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f64_v8i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #144
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 144
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0]
|
|
; NONEON-NOSVE-NEXT: str q1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp q0, q3, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: str q2, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d2, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldr d1, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #104]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #104]
|
|
; NONEON-NOSVE-NEXT: str d2, [sp, #120]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #142]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #140]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #120]
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #138]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #136]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #134]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #132]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #130]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #128]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #144
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x double>, ptr %a
|
|
%res = fptosi <8 x double> %op1 to <8 x i16>
|
|
ret <8 x i16> %res
|
|
}
|
|
|
|
define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v16f64_v16i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #96]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x0, #32]
|
|
; CHECK-NEXT: ldp q4, q5, [x0, #64]
|
|
; CHECK-NEXT: ldp q6, q7, [x0]
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
|
|
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
|
|
; CHECK-NEXT: fcvtzs z7.d, p0/m, z7.d
|
|
; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s
|
|
; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s
|
|
; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s
|
|
; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s
|
|
; CHECK-NEXT: mov z17.s, z1.s[1]
|
|
; CHECK-NEXT: mov z16.s, z3.s[1]
|
|
; CHECK-NEXT: mov z18.s, z0.s[1]
|
|
; CHECK-NEXT: mov z21.s, z2.s[1]
|
|
; CHECK-NEXT: mov z19.s, z5.s[1]
|
|
; CHECK-NEXT: mov z20.s, z4.s[1]
|
|
; CHECK-NEXT: mov z22.s, z7.s[1]
|
|
; CHECK-NEXT: mov z23.s, z6.s[1]
|
|
; CHECK-NEXT: zip1 z1.h, z1.h, z17.h
|
|
; CHECK-NEXT: zip1 z3.h, z3.h, z16.h
|
|
; CHECK-NEXT: zip1 z0.h, z0.h, z18.h
|
|
; CHECK-NEXT: zip1 z2.h, z2.h, z21.h
|
|
; CHECK-NEXT: zip1 z5.h, z5.h, z19.h
|
|
; CHECK-NEXT: zip1 z4.h, z4.h, z20.h
|
|
; CHECK-NEXT: zip1 z7.h, z7.h, z22.h
|
|
; CHECK-NEXT: zip1 z6.h, z6.h, z23.h
|
|
; CHECK-NEXT: zip1 z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: zip1 z2.s, z2.s, z3.s
|
|
; CHECK-NEXT: zip1 z1.s, z4.s, z5.s
|
|
; CHECK-NEXT: zip1 z3.s, z6.s, z7.s
|
|
; CHECK-NEXT: zip1 z0.d, z1.d, z0.d
|
|
; CHECK-NEXT: zip1 z1.d, z3.d, z2.d
|
|
; CHECK-NEXT: stp q1, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v16f64_v16i16:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #304
|
|
; NONEON-NOSVE-NEXT: str x29, [sp, #288] // 8-byte Folded Spill
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 304
|
|
; NONEON-NOSVE-NEXT: .cfi_offset w29, -16
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: ldr x29, [sp, #288] // 8-byte Folded Reload
|
|
; NONEON-NOSVE-NEXT: ldp q6, q7, [x0]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #64]
|
|
; NONEON-NOSVE-NEXT: ldp q4, q5, [x0, #96]
|
|
; NONEON-NOSVE-NEXT: stp q1, q7, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q6, q4, [sp]
|
|
; NONEON-NOSVE-NEXT: stp q5, q3, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #96]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #168]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #184]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #176]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #136]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #152]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #144]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #112]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d2, [sp, #176]
|
|
; NONEON-NOSVE-NEXT: ldr d1, [sp, #168]
|
|
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #232]
|
|
; NONEON-NOSVE-NEXT: ldr d1, [sp, #136]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #192]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #232]
|
|
; NONEON-NOSVE-NEXT: str d2, [sp, #248]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d2, [sp, #144]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #270]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #268]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #248]
|
|
; NONEON-NOSVE-NEXT: stp d1, d0, [sp, #200]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #160]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #266]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #264]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #240]
|
|
; NONEON-NOSVE-NEXT: stp d2, d0, [sp, #216]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #192]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #262]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #260]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #200]
|
|
; NONEON-NOSVE-NEXT: str d0, [sp, #296]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #258]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #256]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #216]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #286]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #284]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #208]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #282]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #280]
|
|
; NONEON-NOSVE-NEXT: ldp w8, w9, [sp, #224]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #276]
|
|
; NONEON-NOSVE-NEXT: ldr w8, [sp, #300]
|
|
; NONEON-NOSVE-NEXT: strh w9, [sp, #278]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #274]
|
|
; NONEON-NOSVE-NEXT: ldr w8, [sp, #296]
|
|
; NONEON-NOSVE-NEXT: strh w8, [sp, #272]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #256]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #304
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <16 x double>, ptr %a
|
|
%res = fptosi <16 x double> %op1 to <16 x i16>
|
|
store <16 x i16> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS D -> S
|
|
;
|
|
|
|
define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v1f64_v1i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: str w8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <1 x double> %op1 to <1 x i32>
|
|
ret <1 x i32> %res
|
|
}
|
|
|
|
define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f64_v2i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #24]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x double> %op1 to <2 x i32>
|
|
ret <2 x i32> %res
|
|
}
|
|
|
|
define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) {
|
|
; CHECK-LABEL: fcvtzs_v4f64_v4i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #40]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #48
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x double>, ptr %a
|
|
%res = fptosi <4 x double> %op1 to <4 x i32>
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v8f64_v8i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0, #32]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: ldp q2, q3, [x0]
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
|
|
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
|
|
; CHECK-NEXT: ptrue p0.s, vl2
|
|
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
|
|
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
|
|
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
|
|
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
|
|
; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s
|
|
; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s
|
|
; CHECK-NEXT: stp q2, q0, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v8f64_v8i32:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0, #32]
|
|
; NONEON-NOSVE-NEXT: str q1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp q3, q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: str q2, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #88]
|
|
; NONEON-NOSVE-NEXT: fcvtzs w9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs w8, d0
|
|
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #80]
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #64]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #96
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <8 x double>, ptr %a
|
|
%res = fptosi <8 x double> %op1 to <8 x i32>
|
|
store <8 x i32> %res, ptr %b
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCVTZS D -> D
|
|
;
|
|
|
|
define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v1f64_v1i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl1
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: sub sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, d0
|
|
; NONEON-NOSVE-NEXT: str x8, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #16
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <1 x double> %op1 to <1 x i64>
|
|
ret <1 x i64> %res
|
|
}
|
|
|
|
define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) {
|
|
; CHECK-LABEL: fcvtzs_v2f64_v2i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, d0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #32
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%res = fptosi <2 x double> %op1 to <2 x i64>
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) {
|
|
; CHECK-LABEL: fcvtzs_v4f64_v4i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: ptrue p0.d, vl2
|
|
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
|
|
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
|
|
; CHECK-NEXT: stp q0, q1, [x1]
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i64:
|
|
; NONEON-NOSVE: // %bb.0:
|
|
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
|
|
; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-64]!
|
|
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, d0
|
|
; NONEON-NOSVE-NEXT: ldp d0, d1, [sp]
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #48]
|
|
; NONEON-NOSVE-NEXT: fcvtzs x9, d1
|
|
; NONEON-NOSVE-NEXT: fcvtzs x8, d0
|
|
; NONEON-NOSVE-NEXT: stp x8, x9, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
|
|
; NONEON-NOSVE-NEXT: stp q0, q1, [x1]
|
|
; NONEON-NOSVE-NEXT: add sp, sp, #64
|
|
; NONEON-NOSVE-NEXT: ret
|
|
%op1 = load <4 x double>, ptr %a
|
|
%res = fptosi <4 x double> %op1 to <4 x i64>
|
|
store <4 x i64> %res, ptr %b
|
|
ret void
|
|
}
|