61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
166 lines
4.8 KiB
LLVM
166 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)
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declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)
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declare i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)
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declare i24 @llvm.vector.reduce.add.v1i24(<1 x i24> %a)
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declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
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declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)
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declare i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)
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declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)
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declare i8 @llvm.vector.reduce.add.v9i8(<9 x i8> %a)
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declare i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)
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declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %a)
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declare i24 @llvm.vector.reduce.add.v4i24(<4 x i24> %a)
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declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)
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declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
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define i1 @test_v1i1(<1 x i1> %a) nounwind {
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; CHECK-LABEL: test_v1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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%b = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)
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ret i1 %b
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}
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define i8 @test_v1i8(<1 x i8> %a) nounwind {
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; CHECK-LABEL: test_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.b[0]
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; CHECK-NEXT: ret
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%b = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)
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ret i8 %b
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}
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define i16 @test_v1i16(<1 x i16> %a) nounwind {
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; CHECK-LABEL: test_v1i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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%b = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)
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ret i16 %b
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}
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define i24 @test_v1i24(<1 x i24> %a) nounwind {
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; CHECK-LABEL: test_v1i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call i24 @llvm.vector.reduce.add.v1i24(<1 x i24> %a)
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ret i24 %b
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}
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define i32 @test_v1i32(<1 x i32> %a) nounwind {
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; CHECK-LABEL: test_v1i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)
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ret i32 %b
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}
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define i64 @test_v1i64(<1 x i64> %a) nounwind {
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; CHECK-LABEL: test_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%b = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)
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ret i64 %b
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}
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define i128 @test_v1i128(<1 x i128> %a) nounwind {
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; CHECK-LABEL: test_v1i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)
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ret i128 %b
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}
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define i8 @test_v3i8(<3 x i8> %a) nounwind {
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; CHECK-LABEL: test_v3i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: mov v0.h[0], w0
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; CHECK-NEXT: mov v0.h[1], w1
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; CHECK-NEXT: mov v0.h[2], w2
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; CHECK-NEXT: addv h0, v0.4h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)
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ret i8 %b
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}
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define i8 @test_v9i8(<9 x i8> %a) nounwind {
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; CHECK-LABEL: test_v9i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI8_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: addv b0, v0.16b
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i8 @llvm.vector.reduce.add.v9i8(<9 x i8> %a)
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ret i8 %b
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}
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define i32 @test_v3i32(<3 x i32> %a) nounwind {
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; CHECK-LABEL: test_v3i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.s[3], wzr
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)
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ret i32 %b
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}
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define i1 @test_v4i1(<4 x i1> %a) nounwind {
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; CHECK-LABEL: test_v4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: addv h0, v0.4h
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%b = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %a)
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ret i1 %b
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}
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define i24 @test_v4i24(<4 x i24> %a) nounwind {
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; CHECK-LABEL: test_v4i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i24 @llvm.vector.reduce.add.v4i24(<4 x i24> %a)
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ret i24 %b
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}
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define i128 @test_v2i128(<2 x i128> %a) nounwind {
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; CHECK-LABEL: test_v2i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adds x0, x0, x2
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; CHECK-NEXT: adc x1, x1, x3
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; CHECK-NEXT: ret
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%b = call i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)
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ret i128 %b
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}
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define i32 @test_v16i32(<16 x i32> %a) nounwind {
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; CHECK-LABEL: test_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%b = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)
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ret i32 %b
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}
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