llvm-project/llvm/test/CodeGen/ARM/and-cmpz-to-shift.ll
Sergei Barannikov e0ed0333f0
Reland "[ARM] Stop gluing ALU nodes to branches / selects" (#118887)
Re-landing #116970 after fixing miscompilation error.

The original change made it possible for CMPZ to have multiple uses;
`ARMDAGToDAGISel::SelectCMPZ` was not prepared for this.

Pull Request: https://github.com/llvm/llvm-project/pull/118887


Original commit message:

Following #116547 and #116676, this PR changes the type of results and
operands of some nodes to accept / return a normal type instead of Glue.

Unfortunately, changing the result type of one node requires changing
the operand types of all potential consumer nodes, which in turn
requires changing the result types of all other possible producer nodes.
So this is a bulk change.
2024-12-07 10:14:36 +03:00

47 lines
1.3 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=T1
; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s --check-prefix=T2
define void @test(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d, ptr %p1, ptr %p2) {
; T1-LABEL: test:
; T1: @ %bb.0:
; T1-NEXT: push {r4, lr}
; T1-NEXT: movs r4, #1
; T1-NEXT: lsls r4, r4, #24
; T1-NEXT: tst r0, r4
; T1-NEXT: beq .LBB0_2
; T1-NEXT: @ %bb.1:
; T1-NEXT: mov r1, r2
; T1-NEXT: .LBB0_2:
; T1-NEXT: ldr r0, [sp, #12]
; T1-NEXT: str r1, [r0]
; T1-NEXT: beq .LBB0_4
; T1-NEXT: @ %bb.3:
; T1-NEXT: ldr r3, [sp, #8]
; T1-NEXT: .LBB0_4:
; T1-NEXT: ldr r0, [sp, #16]
; T1-NEXT: str r3, [r0]
; T1-NEXT: pop {r4, pc}
;
; T2-LABEL: test:
; T2: @ %bb.0:
; T2-NEXT: tst.w r0, #16777216
; T2-NEXT: ldr r0, [sp, #4]
; T2-NEXT: it ne
; T2-NEXT: movne r1, r2
; T2-NEXT: str r1, [r0]
; T2-NEXT: ldr r1, [sp, #8]
; T2-NEXT: ldr r0, [sp]
; T2-NEXT: it eq
; T2-NEXT: moveq r0, r3
; T2-NEXT: str r0, [r1]
; T2-NEXT: bx lr
%and = and i32 %x, u0x1000000
%cmp = icmp eq i32 %and, 0
%sel1 = select i1 %cmp, i32 %a, i32 %b
%sel2 = select i1 %cmp, i32 %c, i32 %d
store i32 %sel1, ptr %p1, align 4
store i32 %sel2, ptr %p2, align 4
ret void
}