9cf68679c4
This test case was failing to compile with a "ran out of registers during register allocation" error at -O0. This was because CMP_SWAP_64 has 3 operands which must be an even-odd register pair, and two other GPR operands. All of the def operands are also early-clobber, so registers can't be shared between uses and defs. Because the function has an over-aligned alloca it needs frame and base pointers, so r6 and r11 are both reserved. That leaves r0/r1, r2/r3, r4/r5 and r8/r9 as the only valid register pairs, and if the two individual GPR operands happen to get allocated to registers in different pairs then only 2 pairs will be available for the three GPRPair operands. To fix this, I've merged the two GPR operands into a single GPRPair operand. This means that the instruction now has 4 GPRPair operands, which can always be allocated without relying on luck. This does constrain register allocation a bit more, but this pseudo instruction is only used at -O0, so I don't think that's a problem.
97 lines
3.7 KiB
LLVM
97 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=armv7-none-eabi -O0 | FileCheck %s --check-prefix=CHECK --check-prefix=LE
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; RUN: llc < %s -mtriple=armv7eb-none-eabi -O0 | FileCheck %s --check-prefix=CHECK --check-prefix=BE
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;; Previously, this failed during register allocation because the CMP_SWAP_64
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;; pseudo-instruction has a lot of operands, many of which need to be even-odd
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;; register pairs, and the over-aligned alloca in this function causes both a
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;; frame pointer and a base pointer to be needed.
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define void @test(ptr %ptr) {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r8, r9, r10, r11, lr}
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; CHECK-NEXT: push {r4, r5, r6, r8, r9, r10, r11, lr}
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; CHECK-NEXT: .setfp r11, sp, #24
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; CHECK-NEXT: add r11, sp, #24
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; CHECK-NEXT: .pad #32
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: bfc sp, #0, #4
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; CHECK-NEXT: mov r6, sp
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; CHECK-NEXT: str r0, [r6, #28] @ 4-byte Spill
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; CHECK-NEXT: b .LBB0_1
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; CHECK-NEXT: .LBB0_1: @ %block1
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; CHECK-NEXT: ldr r0, [r6, #28] @ 4-byte Reload
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; CHECK-NEXT: mov r1, sp
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; CHECK-NEXT: sub r1, r1, #16
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; CHECK-NEXT: bic r1, r1, #15
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; CHECK-NEXT: mov sp, r1
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: ldr r1, [r0]
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; CHECK-NEXT: ldr r0, [r0, #4]
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; CHECK-NEXT: str r1, [r6, #20] @ 4-byte Spill
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; CHECK-NEXT: str r0, [r6, #24] @ 4-byte Spill
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_2: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Loop Header: Depth=1
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; CHECK-NEXT: @ Child Loop BB0_3 Depth 2
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; CHECK-NEXT: ldr r2, [r6, #24] @ 4-byte Reload
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; CHECK-NEXT: ldr r0, [r6, #20] @ 4-byte Reload
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; CHECK-NEXT: ldr r8, [r6, #28] @ 4-byte Reload
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; LE-NEXT: str r2, [r6, #16] @ 4-byte Spill
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; LE-NEXT: str r0, [r6, #12] @ 4-byte Spill
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; BE-NEXT: str r2, [r6, #12] @ 4-byte Spill
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; BE-NEXT: str r0, [r6, #16] @ 4-byte Spill
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; CHECK-NEXT: @ implicit-def: $r1
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; CHECK-NEXT: @ implicit-def: $r3
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; CHECK-NEXT: @ kill: def $r8 killed $r8 def $r8_r9
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: @ kill: def $r0 killed $r0 def $r0_r1
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; CHECK-NEXT: mov r1, r2
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: mov r2, r12
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; CHECK-NEXT: mov r3, r12
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; CHECK-NEXT: .LBB0_3: @ %atomicrmw.start
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; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1
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; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
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; CHECK-NEXT: ldrexd r4, r5, [r8]
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; CHECK-NEXT: cmp r4, r0
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; CHECK-NEXT: cmpeq r5, r1
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; CHECK-NEXT: bne .LBB0_5
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; CHECK-NEXT: @ %bb.4: @ %atomicrmw.start
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; CHECK-NEXT: @ in Loop: Header=BB0_3 Depth=2
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; CHECK-NEXT: strexd r9, r2, r3, [r8]
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; CHECK-NEXT: cmp r9, #0
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; CHECK-NEXT: bne .LBB0_3
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; CHECK-NEXT: .LBB0_5: @ %atomicrmw.start
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; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
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; CHECK-NEXT: ldr r2, [r6, #12] @ 4-byte Reload
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; LE-NEXT: ldr r1, [r6, #16] @ 4-byte Reload
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; LE-NEXT: mov r0, r5
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; LE-NEXT: eor r3, r0, r1
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; LE-NEXT: mov r1, r4
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; LE-NEXT: eor r2, r1, r2
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; BE-NEXT: ldr r0, [r6, #16] @ 4-byte Reload
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; BE-NEXT: mov r1, r4
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; BE-NEXT: eor r3, r1, r0
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; BE-NEXT: mov r0, r5
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; BE-NEXT: eor r2, r0, r2
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; CHECK-NEXT: orr r2, r2, r3
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: str r1, [r6, #20] @ 4-byte Spill
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; CHECK-NEXT: str r0, [r6, #24] @ 4-byte Spill
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; CHECK-NEXT: bne .LBB0_2
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; CHECK-NEXT: b .LBB0_6
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; CHECK-NEXT: .LBB0_6: @ %atomicrmw.end
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: sub sp, r11, #24
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; CHECK-NEXT: pop {r4, r5, r6, r8, r9, r10, r11, pc}
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entry:
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br label %block1
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block1:
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%stuff = alloca i8, i64 16, align 16
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store atomic i64 0, ptr %ptr seq_cst, align 8
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ret void
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}
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