e0ed0333f0
Re-landing #116970 after fixing miscompilation error. The original change made it possible for CMPZ to have multiple uses; `ARMDAGToDAGISel::SelectCMPZ` was not prepared for this. Pull Request: https://github.com/llvm/llvm-project/pull/118887 Original commit message: Following #116547 and #116676, this PR changes the type of results and operands of some nodes to accept / return a normal type instead of Glue. Unfortunately, changing the result type of one node requires changing the operand types of all potential consumer nodes, which in turn requires changing the result types of all other possible producer nodes. So this is a bulk change.
177 lines
5.6 KiB
LLVM
177 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 < %s | FileCheck %s
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define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB0_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrexb r12, [r0]
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; CHECK-NEXT: uxtb r3, r1
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; CHECK-NEXT: cmp r12, r3
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; CHECK-NEXT: mov r3, r12
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; CHECK-NEXT: subhs r3, r3, r1
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; CHECK-NEXT: strexb r2, r3, [r0]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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%result = atomicrmw usub_cond ptr %ptr, i8 %val seq_cst
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ret i8 %result
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}
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define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB1_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrexh r12, [r0]
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; CHECK-NEXT: uxth r3, r1
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; CHECK-NEXT: cmp r12, r3
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; CHECK-NEXT: mov r3, r12
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; CHECK-NEXT: subhs r3, r3, r1
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; CHECK-NEXT: strexh r2, r3, [r0]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB1_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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%result = atomicrmw usub_cond ptr %ptr, i16 %val seq_cst
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ret i16 %result
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}
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define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB2_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrex r12, [r0]
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; CHECK-NEXT: subs r3, r12, r1
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; CHECK-NEXT: movlo r3, r12
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; CHECK-NEXT: strex r2, r3, [r0]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB2_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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%result = atomicrmw usub_cond ptr %ptr, i32 %val seq_cst
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ret i32 %result
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}
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define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r11, lr}
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: mov r12, r0
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB3_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrexd r0, r1, [r12]
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; CHECK-NEXT: subs r4, r0, r2
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; CHECK-NEXT: sbcs r5, r1, r3
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; CHECK-NEXT: movlo r5, r1
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; CHECK-NEXT: movlo r4, r0
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; CHECK-NEXT: strexd lr, r4, r5, [r12]
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; CHECK-NEXT: cmp lr, #0
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; CHECK-NEXT: bne .LBB3_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: pop {r4, r5, r11, pc}
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%result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst
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ret i64 %result
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}
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define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB4_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrexb r12, [r0]
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; CHECK-NEXT: uqsub8 r3, r12, r1
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; CHECK-NEXT: strexb r2, r3, [r0]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB4_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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%result = atomicrmw usub_sat ptr %ptr, i8 %val seq_cst
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ret i8 %result
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}
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define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB5_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrexh r12, [r0]
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; CHECK-NEXT: uqsub16 r3, r12, r1
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; CHECK-NEXT: strexh r2, r3, [r0]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB5_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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%result = atomicrmw usub_sat ptr %ptr, i16 %val seq_cst
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ret i16 %result
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}
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define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB6_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrex r12, [r0]
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; CHECK-NEXT: subs r3, r12, r1
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; CHECK-NEXT: movlo r3, #0
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; CHECK-NEXT: strex r2, r3, [r0]
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB6_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: bx lr
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%result = atomicrmw usub_sat ptr %ptr, i32 %val seq_cst
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ret i32 %result
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}
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define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) {
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; CHECK-LABEL: atomicrmw_usub_sat_i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: .LBB7_1: @ %atomicrmw.start
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldrexd r4, r5, [r0]
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; CHECK-NEXT: subs r6, r4, r2
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; CHECK-NEXT: sbcs r7, r5, r3
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; CHECK-NEXT: adc r1, r12, #0
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; CHECK-NEXT: teq r1, #1
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; CHECK-NEXT: movwne r7, #0
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; CHECK-NEXT: movwne r6, #0
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; CHECK-NEXT: strexd r1, r6, r7, [r0]
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: bne .LBB7_1
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; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: dmb ish
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; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
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%result = atomicrmw usub_sat ptr %ptr, i64 %val seq_cst
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ret i64 %result
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}
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