cbdccb30c2
If a virtual register is not assigned preferred physical register, it means some COPY instructions will be changed to real register move instructions. In this case we can try to split the virtual register in colder blocks, if success, the original COPY instructions can be deleted, and the new COPY instructions in colder blocks will be generated as register move instructions. It results in fewer dynamic register move instructions executed. The new test case split-reg-with-hint.ll gives an example, the hot path contains 24 instructions without this patch, now it is only 4 instructions with this patch. Differential Revision: https://reviews.llvm.org/D156491
260 lines
7.4 KiB
LLVM
260 lines
7.4 KiB
LLVM
; We run the tests with both the default optimization level and O0, to make sure
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; we don't have any ABI differences between them. In principle, the ABI checks
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; should be the same for both optimization levels (there could be exceptions
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; from this when a div and a mod with the same operands are not coallesced into
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; the same divmod, but luckily this doesn't occur in practice even at O0).
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; Sometimes the checks that the correct registers are used after the libcalls
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; are different between optimization levels, so we have to separate them.
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; RUN: llc -mtriple armv7-none-eabi %s -o - | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-none-eabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-none-eabihf %s -o - | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-none-eabihf %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI
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; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
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; RUN: llc -mtriple armv7-linux-androideabi %s -o - | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-linux-androideabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-linux-gnueabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-linux-musleabi %s -o - | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-linux-musleabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI
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; RUN: llc -mtriple armv7-apple-darwin %s -o - | FileCheck %s --check-prefixes=DARWIN
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; RUN: llc -mtriple armv7-apple-darwin %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=DARWIN-O0
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; RUN: llc -mtriple thumbv7-windows %s -o - | FileCheck %s --check-prefixes=WINDOWS,WINDOWS-DEFAULT
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; RUN: llc -mtriple thumbv7-windows %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefixes=WINDOWS,WINDOWS-O0
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define signext i16 @f16(i16 signext %a, i16 signext %b) {
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; EABI-LABEL: f16:
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; DARWIN-LABEL: f16:
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; DARWIN-O0-LABEL: f16:
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; WINDOWS-LABEL: f16:
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entry:
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%conv = sext i16 %a to i32
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%conv1 = sext i16 %b to i32
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%div = sdiv i32 %conv, %conv1
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%rem = srem i32 %conv, %conv1
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; EABI: __aeabi_idivmod
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; EABI: mov [[div:r[0-9]+]], r0
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; EABI: mov [[rem:r[0-9]+]], r1
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; DARWIN: __divmodsi4
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; DARWIN-O0: __divsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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; WINDOWS: __rt_sdiv
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; WINDOWS-DEFAULT: add [[sum:r[0-9]+]], r1
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; WINDOWS-O0: mov [[rem:r[0-9]+]], r1
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%rem8 = srem i32 %conv1, %conv
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; EABI: __aeabi_idivmod
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; DARWIN: __modsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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%add = add nsw i32 %rem, %div
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%add13 = add nsw i32 %add, %rem8
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%conv14 = trunc i32 %add13 to i16
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; EABI: add r0{{.*}}r1
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; EABI: sxth r0, r0
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; WINDOWS-DEFAULT: adds [[sum1:r[0-9]+]], [[sum]], r1
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; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]],
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; WINDOWS-O0: add [[sum1:r[0-9]+]], r1
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; WINDOWS: sxth [[res:r[0-9]+]], [[sum1]]
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ret i16 %conv14
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}
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define i32 @f32(i32 %a, i32 %b) {
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; EABI-LABEL: f32:
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; DARWIN-LABEL: f32:
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; DARWIN-O0-LABEL: f32:
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; WINDOWS-LABEL: f32:
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entry:
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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; EABI: __aeabi_idivmod
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; EABI: mov [[div:r[0-9]+]], r0
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; EABI: mov [[rem:r[0-9]+]], r1
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; DARWIN: ___divmodsi4
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; DARWIN-O0: __divsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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; WINDOWS: mov [[div:r[0-9]+]], r0
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; WINDOWS: __rt_sdiv
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; WINDOWS-DEFAULT: add [[div]], r1
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%rem1 = srem i32 %b, %a
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; EABI: __aeabi_idivmod
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; DARWIN: __modsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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%add = add nsw i32 %rem, %div
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%add2 = add nsw i32 %add, %rem1
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; EABI: add r0{{.*}}r1
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; WINDOWS-DEFAULT: adds r0, [[div]], r1
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; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]]
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; WINDOWS-O0: add [[sum]], r1
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ret i32 %add2
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}
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define i32 @uf(i32 %a, i32 %b) {
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; EABI-LABEL: uf:
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; DARWIN-LABEL: uf:
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; DARWIN-O0-LABEL: uf:
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; WINDOWS-LABEL: uf:
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entry:
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%div = udiv i32 %a, %b
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%rem = urem i32 %a, %b
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; EABI: __aeabi_uidivmod
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; DARWIN: __udivmodsi4
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; DARWIN-O0: __udivsi3
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; DARWIN-O0: __umodsi3
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; WINDOWS: __rt_udiv
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; WINDOWS: mov [[div:r[0-9]+]], r0
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; WINDOWS: __rt_udiv
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; WINDOWS-DEFAULT: add [[div]], r1
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%rem1 = urem i32 %b, %a
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; EABI: __aeabi_uidivmod
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; DARWIN: __umodsi3
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; DARWIN-O0: __umodsi3
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; WINDOWS: __rt_udiv
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%add = add nuw i32 %rem, %div
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%add2 = add nuw i32 %add, %rem1
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; EABI: add r0{{.*}}r1
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; WINDOWS-DEFAULT: adds [[sum:r[0-9]+]], [[div]], r1
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; WINDOWS-O0: adds [[sum:r[0-9]+]],
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; WINDOWS-O0: add [[sum]], r1
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ret i32 %add2
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}
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define i64 @longf(i64 %a, i64 %b) {
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; EABI-LABEL: longf:
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; DARWIN-LABEL: longf:
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; DARWIN-O0-LABEL: longf:
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; WINDOWS-LABEL: longf:
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entry:
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%div = sdiv i64 %a, %b
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%rem = srem i64 %a, %b
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; EABI: __aeabi_ldivmod
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; EABI-NEXT: adds r0
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; EABI-NEXT: adc r1
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; EABI-NOT: __aeabi_ldivmod
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; DARWIN: ___divdi3
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; DARWIN: mov [[div1:r[0-9]+]], r0
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; DARWIN: mov [[div2:r[0-9]+]], r1
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; DARWIN: __moddi3
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; DARWIN-O0: __divdi3
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; DARWIN-O0: __moddi3
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; WINDOWS: __rt_sdiv64
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%add = add nsw i64 %rem, %div
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; DARWIN: adds r0{{.*}}[[div1]]
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; DARWIN: adc r1{{.*}}[[div2]]
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; WINDOWS: adds r0, r0, r2
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; WINDOWS: adcs r1, r3
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ret i64 %add
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}
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define i16 @shortf(i16 %a, i16 %b) {
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; EABI-LABEL: shortf:
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; DARWIN-LABEL: shortf:
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; DARWIN-O0-LABEL: shortf:
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; WINDOWS-LABEL: shortf:
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entry:
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%div = sdiv i16 %a, %b
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%rem = srem i16 %a, %b
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; EABI: __aeabi_idivmod
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; DARWIN: ___divmodsi4
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; DARWIN-O0: __divmodsi4
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; WINDOWS: __rt_sdiv
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; WINDOWS: mov [[div:r[0-9]+]], r0
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; WINDOWS: __rt_sdiv
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%add = add nsw i16 %rem, %div
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; EABI: add r0, r1
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; WINDOWS: adds r0, r1, [[div]]
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ret i16 %add
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}
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define i32 @g1(i32 %a, i32 %b) {
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; EABI-LABEL: g1:
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; DARWIN-LABEL: g1:
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; DARWIN-O0-LABEL: g1:
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; WINDOWS-LABEL: g1:
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entry:
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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; EABI: __aeabi_idivmod
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; DARWIN: ___divmodsi4
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; DARWIN-O0: __divsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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; WINDOWS: mov [[div:r[0-9]+]], r0
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; WINDOWS: __rt_sdiv
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%add = add nsw i32 %rem, %div
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; EABI: add r0{{.*}}r1
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; WINDOWS: adds r0, r1, [[div]]
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ret i32 %add
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}
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; On both Darwin and Gnu, this is just a call to __modsi3
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define i32 @g2(i32 %a, i32 %b) {
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; EABI-LABEL: g2:
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; DARWIN-LABEL: g2:
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; DARWIN-O0-LABEL: g2:
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; WINDOWS-LABEL: g2:
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entry:
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%rem = srem i32 %a, %b
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; EABI: __aeabi_idivmod
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; DARWIN: __modsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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ret i32 %rem
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; EABI: mov r0, r1
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; WINDOWS: mov r0, r1
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}
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define i32 @g3(i32 %a, i32 %b) {
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; EABI-LABEL: g3:
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; DARWIN-LABEL: g3:
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; DARWIN-O0-LABEL: g3:
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; WINDOWS-LABEL: g3:
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entry:
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%rem = srem i32 %a, %b
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; EABI: __aeabi_idivmod
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; EABI: mov [[mod:r[0-9]+]], r1
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; DARWIN: __modsi3
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; DARWIN: mov [[sum:r[0-9]+]], r0
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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; WINDOWS: mov [[arg:r[0-9]+]], r1
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; WINDOWS: mov [[rem:r[0-9]+]], r1
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%rem1 = srem i32 %b, %rem
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; EABI: __aeabi_idivmod
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; DARWIN: __modsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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%add = add nsw i32 %rem1, %rem
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; EABI: add r0, r1, [[mod]]
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; DARWIN: add r0{{.*}}[[sum]]
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; WINDOWS: adds r0, r1, [[rem]]
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ret i32 %add
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}
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define i32 @g4(i32 %a, i32 %b) {
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; EABI-LABEL: g4:
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; DARWIN-LABEL: g4:
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; DARWIN-O0-LABEL: g4:
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; WINDOWS-LABEL: g4:
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entry:
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%div = sdiv i32 %a, %b
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; EABI: __aeabi_idiv{{$}}
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; EABI: mov [[div:r[0-9]+]], r0
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; DARWIN: ___divsi3
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; DARWIN: mov [[sum:r[0-9]+]], r0
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; DARWIN-O0: __divsi3
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; WINDOWS: __rt_sdiv
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; WINDOWS: mov [[div:r[0-9]+]], r0
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%rem = srem i32 %b, %div
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; EABI: __aeabi_idivmod
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; DARWIN: __modsi3
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; DARWIN-O0: __modsi3
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; WINDOWS: __rt_sdiv
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%add = add nsw i32 %rem, %div
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; EABI: add r0, r1, [[div]]
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; DARWIN: add r0{{.*}}[[sum]]
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; WINDOWS: adds r0, r1, [[div]]
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ret i32 %add
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}
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