e0ed0333f0
Re-landing #116970 after fixing miscompilation error. The original change made it possible for CMPZ to have multiple uses; `ARMDAGToDAGISel::SelectCMPZ` was not prepared for this. Pull Request: https://github.com/llvm/llvm-project/pull/118887 Original commit message: Following #116547 and #116676, this PR changes the type of results and operands of some nodes to accept / return a normal type instead of Glue. Unfortunately, changing the result type of one node requires changing the operand types of all potential consumer nodes, which in turn requires changing the result types of all other possible producer nodes. So this is a bulk change.
321 lines
9.4 KiB
LLVM
321 lines
9.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 | FileCheck %s --check-prefixes=CHECK,SCALAR
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v6t2 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,NEON
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; When first 2 operands match, it's a rotate.
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define i8 @rotl_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotl_i8_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r1, r0
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; CHECK-NEXT: lsl r0, r0, #3
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; CHECK-NEXT: orr r0, r0, r1, lsr #5
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; CHECK-NEXT: bx lr
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%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i64 @rotl_i64_const_shift(i64 %x) {
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; CHECK-LABEL: rotl_i64_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsl r2, r0, #3
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; CHECK-NEXT: orr r2, r2, r1, lsr #29
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; CHECK-NEXT: lsl r1, r1, #3
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; CHECK-NEXT: orr r1, r1, r0, lsr #29
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
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ret i64 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotl_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotl_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r2, r1, #15
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: and r1, r1, #15
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; CHECK-NEXT: lsl r2, r0, r2
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: orr r0, r2, r0, lsr r1
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; CHECK-NEXT: bx lr
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%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotl_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotl_i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: ror r0, r0, r1
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotl_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotl_i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: tst r2, #32
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; CHECK-NEXT: mov r3, r0
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; CHECK-NEXT: and r12, r2, #31
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; CHECK-NEXT: movne r3, r1
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; CHECK-NEXT: movne r1, r0
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; CHECK-NEXT: mov r4, #31
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; CHECK-NEXT: bic r2, r4, r2
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; CHECK-NEXT: lsl lr, r3, r12
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; CHECK-NEXT: lsr r0, r1, #1
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; CHECK-NEXT: lsl r1, r1, r12
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; CHECK-NEXT: lsr r3, r3, #1
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; CHECK-NEXT: orr r0, lr, r0, lsr r2
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; CHECK-NEXT: orr r1, r1, r3, lsr r2
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; CHECK-NEXT: pop {r4, pc}
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; SCALAR-LABEL: rotl_v4i32:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ldr r12, [sp]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r0, r0, r12
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; SCALAR-NEXT: ldr r12, [sp, #4]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r1, r1, r12
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; SCALAR-NEXT: ldr r12, [sp, #8]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r2, r2, r12
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; SCALAR-NEXT: ldr r12, [sp, #12]
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; SCALAR-NEXT: rsb r12, r12, #0
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; SCALAR-NEXT: ror r3, r3, r12
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotl_v4i32:
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; NEON: @ %bb.0:
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; NEON-NEXT: mov r12, sp
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; NEON-NEXT: vld1.64 {d16, d17}, [r12]
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; NEON-NEXT: vmov.i32 q10, #0x1f
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; NEON-NEXT: vneg.s32 q9, q8
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; NEON-NEXT: vmov d23, r2, r3
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; NEON-NEXT: vand q9, q9, q10
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; NEON-NEXT: vand q8, q8, q10
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; NEON-NEXT: vmov d22, r0, r1
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; NEON-NEXT: vneg.s32 q9, q9
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; NEON-NEXT: vshl.u32 q8, q11, q8
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; NEON-NEXT: vshl.u32 q9, q11, q9
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {
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; SCALAR-LABEL: rotl_v4i32_rotl_const_shift:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ror r0, r0, #29
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; SCALAR-NEXT: ror r1, r1, #29
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; SCALAR-NEXT: ror r2, r2, #29
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; SCALAR-NEXT: ror r3, r3, #29
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotl_v4i32_rotl_const_shift:
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; NEON: @ %bb.0:
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; NEON-NEXT: vmov d17, r2, r3
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; NEON-NEXT: vmov d16, r0, r1
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; NEON-NEXT: vshr.u32 q9, q8, #29
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; NEON-NEXT: vshl.i32 q8, q8, #3
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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; Repeat everything for funnel shift right.
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; When first 2 operands match, it's a rotate.
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define i8 @rotr_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotr_i8_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb r1, r0
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; CHECK-NEXT: lsr r1, r1, #3
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; CHECK-NEXT: orr r0, r1, r0, lsl #5
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; CHECK-NEXT: bx lr
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%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i32 @rotr_i32_const_shift(i32 %x) {
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; CHECK-LABEL: rotr_i32_const_shift:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, #3
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
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ret i32 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotr_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotr_i16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r2, r1, #15
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; CHECK-NEXT: rsb r1, r1, #0
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; CHECK-NEXT: and r1, r1, #15
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; CHECK-NEXT: uxth r3, r0
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; CHECK-NEXT: lsr r2, r3, r2
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; CHECK-NEXT: orr r0, r2, r0, lsl r1
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; CHECK-NEXT: bx lr
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%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotr_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotr_i32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ror r0, r0, r1
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotr_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotr_i64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: tst r2, #32
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; CHECK-NEXT: mov r3, r1
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; CHECK-NEXT: moveq r3, r0
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; CHECK-NEXT: moveq r0, r1
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; CHECK-NEXT: mov r1, #31
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; CHECK-NEXT: lsl r12, r0, #1
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; CHECK-NEXT: bic r1, r1, r2
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; CHECK-NEXT: and r2, r2, #31
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; CHECK-NEXT: lsl r12, r12, r1
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; CHECK-NEXT: orr r12, r12, r3, lsr r2
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; CHECK-NEXT: lsl r3, r3, #1
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; CHECK-NEXT: lsl r1, r3, r1
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; CHECK-NEXT: orr r1, r1, r0, lsr r2
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: bx lr
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; SCALAR-LABEL: rotr_v4i32:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ldr r12, [sp]
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; SCALAR-NEXT: ror r0, r0, r12
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; SCALAR-NEXT: ldr r12, [sp, #4]
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; SCALAR-NEXT: ror r1, r1, r12
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; SCALAR-NEXT: ldr r12, [sp, #8]
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; SCALAR-NEXT: ror r2, r2, r12
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; SCALAR-NEXT: ldr r12, [sp, #12]
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; SCALAR-NEXT: ror r3, r3, r12
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotr_v4i32:
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; NEON: @ %bb.0:
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; NEON-NEXT: mov r12, sp
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; NEON-NEXT: vld1.64 {d16, d17}, [r12]
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; NEON-NEXT: vmov.i32 q9, #0x1f
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; NEON-NEXT: vneg.s32 q10, q8
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; NEON-NEXT: vand q8, q8, q9
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; NEON-NEXT: vmov d23, r2, r3
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; NEON-NEXT: vand q9, q10, q9
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; NEON-NEXT: vneg.s32 q8, q8
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; NEON-NEXT: vmov d22, r0, r1
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; NEON-NEXT: vshl.u32 q9, q11, q9
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; NEON-NEXT: vshl.u32 q8, q11, q8
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
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; SCALAR-LABEL: rotr_v4i32_const_shift:
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; SCALAR: @ %bb.0:
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; SCALAR-NEXT: ror r0, r0, #3
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; SCALAR-NEXT: ror r1, r1, #3
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; SCALAR-NEXT: ror r2, r2, #3
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; SCALAR-NEXT: ror r3, r3, #3
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; SCALAR-NEXT: bx lr
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;
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; NEON-LABEL: rotr_v4i32_const_shift:
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; NEON: @ %bb.0:
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; NEON-NEXT: vmov d17, r2, r3
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; NEON-NEXT: vmov d16, r0, r1
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; NEON-NEXT: vshl.i32 q9, q8, #29
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; NEON-NEXT: vshr.u32 q8, q8, #3
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; NEON-NEXT: vorr q8, q8, q9
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; NEON-NEXT: vmov r0, r1, d16
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; NEON-NEXT: vmov r2, r3, d17
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; NEON-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
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}
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define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: bx lr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
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}
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define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
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; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
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; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: bx lr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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