20b2d11896
After https://reviews.llvm.org/rGff4027d152d0 and https://reviews.llvm.org/rG7d15212b8c0c we saw crashes in SelectionDAG when trying to use these constraints when you don't have the fp16 or bf16 extensions. However, it is still possible to move 16-bit floating point values into the right place in S registers with a normal `vmov`, even if we don't have fp16 instructions we can use within the inline assembly string. This patch therefore fixes the crash. I think the reason we weren't getting this crash before is because I think the __fp16 and __bf16 types got an error diagnostic in the Clang frontend when you didn't have the right architectural extensions to use them. This restriction was recently relaxed. The approach for bf16 needs a bit more explanation. Exactly how BF16 is legalized was changed in rGb769eb02b526e3966847351e15d283514c2ec767 - effectively, whether you have the right instructions to get a bf16 value into/out of a S register with MoveTo/FromHPR depends on hasFullFP16, but whether you use a HPR for a value of type MVT::bf16 depends on hasBF16. This is why the tests are not changed by `+bf16` vs `-bf16`, but I've left both sets of RUN lines in case this changes in the future. Test Changes: - Added more testing for testing inline asm (the core part) - fp16-promote.ll and pr47454.ll show improvements where unnecessary fp16-fp32 up/down-casts are no longer emitted. This results in fewer libcalls where those casts would be done with a libcall. - aes-erratum-fix.ll is fairly noisy, and I need to revisit this test so that the IR is more minimal than it is right now, because most of the changes in this commit do not relate to what AES is actually trying to verify. Differential Revision: https://reviews.llvm.org/D143711
36 lines
1.2 KiB
LLVM
36 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=armv8-unknown-linux-unknown -mattr=-fp16 -O0 < %s | FileCheck %s
|
|
|
|
declare fastcc half @getConstant()
|
|
|
|
declare fastcc i1 @isEqual(half %0, half %1)
|
|
|
|
define internal fastcc void @main() {
|
|
; CHECK-LABEL: main:
|
|
; CHECK: @ %bb.0: @ %Entry
|
|
; CHECK-NEXT: push {r11, lr}
|
|
; CHECK-NEXT: mov r11, sp
|
|
; CHECK-NEXT: sub sp, sp, #8
|
|
; CHECK-NEXT: mov r0, #31744
|
|
; CHECK-NEXT: strh r0, [r11, #-2]
|
|
; CHECK-NEXT: ldrh r0, [r11, #-2]
|
|
; CHECK-NEXT: vmov s0, r0
|
|
; CHECK-NEXT: vstr s0, [sp] @ 4-byte Spill
|
|
; CHECK-NEXT: bl getConstant
|
|
; CHECK-NEXT: vmov.f32 s1, s0
|
|
; CHECK-NEXT: vldr s0, [sp] @ 4-byte Reload
|
|
; CHECK-NEXT: bl isEqual
|
|
; CHECK-NEXT: mov sp, r11
|
|
; CHECK-NEXT: pop {r11, pc}
|
|
Entry:
|
|
; First arg directly from constant
|
|
%const = alloca half, align 2
|
|
store half 0xH7C00, ptr %const, align 2
|
|
%arg1 = load half, ptr %const, align 2
|
|
; Second arg from fucntion return
|
|
%arg2 = call fastcc half @getConstant()
|
|
; Arguments should have equivalent mangling
|
|
%result = call fastcc i1 @isEqual(half %arg1, half %arg2)
|
|
ret void
|
|
}
|