d10f23a25d
This changes the lowering of saddsat and ssubsat so that instead of using: r,o = saddo x, y c = setcc r < 0 s = c ? INTMAX : INTMIN ret o ? s : r into using asr and xor to materialize the INTMAX/INTMIN constants: r,o = saddo x, y s = ashr r, BW-1 x = xor s, INTMIN ret o ? x : r https://alive2.llvm.org/ce/z/TYufgD This seems to reduce the instruction count in most testcases across most architectures. X86 has some custom lowering added to compensate for cases where it can increase instruction count. Differential Revision: https://reviews.llvm.org/D105853
115 lines
3.7 KiB
LLVM
115 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2NODSP
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2DSP
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; RUN: llc < %s -mtriple=armv5te-none-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
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; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
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define i32 @qdadd(i32 %x, i32 %y) nounwind {
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; CHECK-T2NODSP-LABEL: qdadd:
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; CHECK-T2NODSP: @ %bb.0:
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; CHECK-T2NODSP-NEXT: adds r0, r0, r0
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; CHECK-T2NODSP-NEXT: mov.w r2, #-2147483648
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: adds r0, r0, r1
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: bx lr
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;
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; CHECK-T2DSP-LABEL: qdadd:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: qdadd r0, r1, r0
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; CHECK-T2DSP-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: qdadd:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: qdadd r0, r1, r0
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; CHECK-ARM-NEXT: bx lr
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %z, i32 %y)
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ret i32 %tmp
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}
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define i32 @qdadd_c(i32 %x, i32 %y) nounwind {
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; CHECK-T2NODSP-LABEL: qdadd_c:
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; CHECK-T2NODSP: @ %bb.0:
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; CHECK-T2NODSP-NEXT: adds r0, r0, r0
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; CHECK-T2NODSP-NEXT: mov.w r2, #-2147483648
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: adds r0, r0, r1
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: bx lr
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;
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; CHECK-T2DSP-LABEL: qdadd_c:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: qdadd r0, r1, r0
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; CHECK-T2DSP-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: qdadd_c:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: qdadd r0, r1, r0
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; CHECK-ARM-NEXT: bx lr
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %y, i32 %z)
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ret i32 %tmp
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}
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define i32 @qdsub(i32 %x, i32 %y) nounwind {
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; CHECK-T2NODSP-LABEL: qdsub:
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; CHECK-T2NODSP: @ %bb.0:
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; CHECK-T2NODSP-NEXT: adds r0, r0, r0
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; CHECK-T2NODSP-NEXT: mov.w r2, #-2147483648
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: subs r0, r1, r0
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: bx lr
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;
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; CHECK-T2DSP-LABEL: qdsub:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: qdsub r0, r1, r0
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; CHECK-T2DSP-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: qdsub:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: qdsub r0, r1, r0
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; CHECK-ARM-NEXT: bx lr
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %y, i32 %z)
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ret i32 %tmp
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}
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define i32 @qdsub_c(i32 %x, i32 %y) nounwind {
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; CHECK-T2NODSP-LABEL: qdsub_c:
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; CHECK-T2NODSP: @ %bb.0:
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; CHECK-T2NODSP-NEXT: adds r0, r0, r0
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; CHECK-T2NODSP-NEXT: mov.w r2, #-2147483648
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: subs r0, r0, r1
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; CHECK-T2NODSP-NEXT: it vs
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; CHECK-T2NODSP-NEXT: eorvs.w r0, r2, r0, asr #31
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; CHECK-T2NODSP-NEXT: bx lr
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;
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; CHECK-T2DSP-LABEL: qdsub_c:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: qadd r0, r0, r0
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; CHECK-T2DSP-NEXT: qsub r0, r0, r1
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; CHECK-T2DSP-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: qdsub_c:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: qadd r0, r0, r0
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; CHECK-ARM-NEXT: qsub r0, r0, r1
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; CHECK-ARM-NEXT: bx lr
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %z, i32 %y)
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ret i32 %tmp
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}
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i32 @llvm.ssub.sat.i32(i32, i32)
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