e0ed0333f0
Re-landing #116970 after fixing miscompilation error. The original change made it possible for CMPZ to have multiple uses; `ARMDAGToDAGISel::SelectCMPZ` was not prepared for this. Pull Request: https://github.com/llvm/llvm-project/pull/118887 Original commit message: Following #116547 and #116676, this PR changes the type of results and operands of some nodes to accept / return a normal type instead of Glue. Unfortunately, changing the result type of one node requires changing the operand types of all potential consumer nodes, which in turn requires changing the result types of all other possible producer nodes. So this is a bulk change.
74 lines
2.1 KiB
LLVM
74 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
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; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix=EXPAND
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define i64 @test_shl(i64 %val, i64 %amt) {
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; CHECK-LABEL: test_shl:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: lsr r3, r0, r3
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; CHECK-NEXT: orr r1, r3, r1, lsl r2
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; CHECK-NEXT: subs r3, r2, #32
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; CHECK-NEXT: lslpl r1, r0, r3
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; CHECK-NEXT: lsl r0, r0, r2
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; CHECK-NEXT: movpl r0, #0
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; CHECK-NEXT: mov pc, lr
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;
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; EXPAND-LABEL: test_shl:
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; EXPAND: @ %bb.0:
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; EXPAND-NEXT: .save {r7, lr}
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; EXPAND-NEXT: push {r7, lr}
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; EXPAND-NEXT: bl __aeabi_llsl
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; EXPAND-NEXT: pop {r7, pc}
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%res = shl i64 %val, %amt
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ret i64 %res
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}
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; Explanation for lshr is pretty much the reverse of shl.
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define i64 @test_lshr(i64 %val, i64 %amt) {
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; CHECK-LABEL: test_lshr:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: lsr r0, r0, r2
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; CHECK-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-NEXT: subs r3, r2, #32
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; CHECK-NEXT: lsrpl r0, r1, r3
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; CHECK-NEXT: lsr r1, r1, r2
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; CHECK-NEXT: movpl r1, #0
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; CHECK-NEXT: mov pc, lr
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;
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; EXPAND-LABEL: test_lshr:
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; EXPAND: @ %bb.0:
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; EXPAND-NEXT: .save {r7, lr}
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; EXPAND-NEXT: push {r7, lr}
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; EXPAND-NEXT: bl __aeabi_llsr
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; EXPAND-NEXT: pop {r7, pc}
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%res = lshr i64 %val, %amt
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ret i64 %res
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}
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; One minor difference for ashr: the high bits must be "hi >> 31" if the shift
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; amount is large to get the right sign bit.
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define i64 @test_ashr(i64 %val, i64 %amt) {
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; CHECK-LABEL: test_ashr:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: lsr r0, r0, r2
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; CHECK-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-NEXT: subs r3, r2, #32
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; CHECK-NEXT: asr r2, r1, r2
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; CHECK-NEXT: asrpl r2, r1, #31
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; CHECK-NEXT: asrpl r0, r1, r3
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; CHECK-NEXT: mov r1, r2
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; CHECK-NEXT: mov pc, lr
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;
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; EXPAND-LABEL: test_ashr:
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; EXPAND: @ %bb.0:
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; EXPAND-NEXT: .save {r7, lr}
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; EXPAND-NEXT: push {r7, lr}
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; EXPAND-NEXT: bl __aeabi_lasr
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; EXPAND-NEXT: pop {r7, pc}
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%res = ashr i64 %val, %amt
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ret i64 %res
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}
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