888f84f72c
This prevents it CSEing multiple nodes together from "volatile" registers as they would end up with the same chain. The new chain out should be the chain from the new READ_REGISTER node. Fixes #144845
125 lines
3.4 KiB
LLVM
125 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=ACORE
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; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=ARM --check-prefix=MCORE
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define i32 @read_i32_encoded_register() nounwind {
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; ARM-LABEL: read_i32_encoded_register:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mrc p1, #2, r0, c3, c4, #5
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; ARM-NEXT: bx lr
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entry:
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%reg = call i32 @llvm.read_register.i32(metadata !0)
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ret i32 %reg
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}
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define i64 @read_i64_encoded_register() nounwind {
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; ARM-LABEL: read_i64_encoded_register:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mrrc p1, #2, r0, r1, c3
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; ARM-NEXT: bx lr
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entry:
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%reg = call i64 @llvm.read_register.i64(metadata !1)
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ret i64 %reg
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}
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define i64 @read_volatile_i64_twice() {
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; ACORE-LABEL: read_volatile_i64_twice:
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; ACORE: @ %bb.0: @ %entry
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; ACORE-NEXT: mrrc p15, #1, r0, r1, c14
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; ACORE-NEXT: mrrc p15, #1, r2, r3, c14
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; ACORE-NEXT: eor r0, r2, r0
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; ACORE-NEXT: eor r1, r3, r1
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; ACORE-NEXT: bx lr
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;
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; MCORE-LABEL: read_volatile_i64_twice:
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; MCORE: @ %bb.0: @ %entry
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; MCORE-NEXT: mrrc p15, #1, r0, r1, c14
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; MCORE-NEXT: mrrc p15, #1, r2, r3, c14
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; MCORE-NEXT: eors r0, r2
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; MCORE-NEXT: eors r1, r3
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; MCORE-NEXT: bx lr
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entry:
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%0 = tail call i64 @llvm.read_volatile_register.i64(metadata !5)
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%1 = tail call i64 @llvm.read_volatile_register.i64(metadata !5)
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%xor = xor i64 %1, %0
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ret i64 %xor
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}
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define i32 @read_apsr() nounwind {
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; ARM-LABEL: read_apsr:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mrs r0, apsr
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; ARM-NEXT: bx lr
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entry:
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%reg = call i32 @llvm.read_register.i32(metadata !2)
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ret i32 %reg
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}
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define i32 @read_fpscr() nounwind {
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; ARM-LABEL: read_fpscr:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: vmrs r0, fpscr
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; ARM-NEXT: bx lr
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entry:
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%reg = call i32 @llvm.read_register.i32(metadata !3)
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ret i32 %reg
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}
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define void @write_i32_encoded_register(i32 %x) nounwind {
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; ARM-LABEL: write_i32_encoded_register:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mcr p1, #2, r0, c3, c4, #5
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; ARM-NEXT: bx lr
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entry:
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call void @llvm.write_register.i32(metadata !0, i32 %x)
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ret void
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}
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define void @write_i64_encoded_register(i64 %x) nounwind {
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; ARM-LABEL: write_i64_encoded_register:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: mcrr p1, #2, r0, r1, c3
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; ARM-NEXT: bx lr
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entry:
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call void @llvm.write_register.i64(metadata !1, i64 %x)
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ret void
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}
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define void @write_apsr(i32 %x) nounwind {
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; ACORE-LABEL: write_apsr:
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; ACORE: @ %bb.0: @ %entry
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; ACORE-NEXT: msr APSR_nzcvq, r0
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; ACORE-NEXT: bx lr
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;
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; MCORE-LABEL: write_apsr:
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; MCORE: @ %bb.0: @ %entry
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; MCORE-NEXT: msr apsr_nzcvq, r0
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; MCORE-NEXT: bx lr
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entry:
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call void @llvm.write_register.i32(metadata !4, i32 %x)
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ret void
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}
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define void @write_fpscr(i32 %x) nounwind {
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; ARM-LABEL: write_fpscr:
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; ARM: @ %bb.0: @ %entry
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; ARM-NEXT: vmsr fpscr, r0
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; ARM-NEXT: bx lr
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entry:
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call void @llvm.write_register.i32(metadata !3, i32 %x)
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ret void
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}
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declare i32 @llvm.read_register.i32(metadata) nounwind
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declare i64 @llvm.read_register.i64(metadata) nounwind
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declare void @llvm.write_register.i32(metadata, i32) nounwind
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declare void @llvm.write_register.i64(metadata, i64) nounwind
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!0 = !{!"cp1:2:c3:c4:5"}
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!1 = !{!"cp1:2:c3"}
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!2 = !{!"apsr"}
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!3 = !{!"fpscr"}
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!4 = !{!"apsr_nzcvq"}
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!5 = !{!"cp15:1:c14"}
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