e63455d5e0
On some architectures such as Arm and X86 the encoding for a nop may change depending on the subtarget in operation at the time of encoding. This change replaces the per module MCSubtargetInfo retained by the targets AsmBackend in favour of passing through the local MCSubtargetInfo in operation at the time. On Arm using the architectural NOP instruction can have a performance benefit on some implementations. For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo to limit the chances of this causing problems in the future. I've not done this for other targets such as X86 as there is more frequent use of the MCSubtargetInfo and it looks to be for stable properties that we would not expect to vary per function. This change required threading STI through MCNopsFragment and MCBoundaryAlignFragment. I've attempted to take into account the in tree experimental backends. Differential Revision: https://reviews.llvm.org/D45962
40 lines
1.0 KiB
LLVM
40 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=arm-linux-gnueabihf -filetype=obj <%s | llvm-objdump --triple=armv7 --no-show-raw-insn -d - | FileCheck %s
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;; Expect architectural nop to be used between func2 and func3 but not func1
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;; and func2 due to lack of subtarget support in func2.
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define i32 @func1() #0 align 16 {
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entry:
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ret i32 0
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}
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define i32 @func2() #1 align 16 {
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entry:
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ret i32 0
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}
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define i32 @func3() #0 align 16 {
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entry:
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ret i32 0
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}
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attributes #0 = { "target-cpu"="generic" "target-features"="+armv7-a,+dsp,+neon,+vfp3,-thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { "target-cpu"="arm7tdmi" "target-features"="+armv4t" "use-soft-float"="true" }
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; CHECK: 00000000 <func1>:
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; CHECK-NEXT: 0: mov r0, #0
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; CHECK-NEXT: 4: bx lr
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; CHECK-NEXT: 8: mov r0, r0
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; CHECK-NEXT: c: mov r0, r0
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; CHECK: 00000010 <func2>:
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; CHECK-NEXT: 10: mov r0, #0
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; CHECK-NEXT: 14: bx lr
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; CHECK-NEXT: 18: nop
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; CHECK-NEXT: 1c: nop
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; CHECK: 00000020 <func3>:
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; CHECK-NEXT: 20: mov r0, #0
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; CHECK-NEXT: 24: bx lr
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