7852ebc088
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
100 lines
3.0 KiB
LLVM
100 lines
3.0 KiB
LLVM
; RUN: llc -mtriple=bpfel -mcpu=v1 -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-EL %s
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; RUN: llc -mtriple=bpfeb -mcpu=v1 -filetype=obj -o - %s | llvm-objdump --no-print-imm-hex -d - | FileCheck --check-prefix=CHECK-EB %s
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; Function Attrs: nounwind uwtable
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define i32 @ld_b(i64 %foo, ptr nocapture %bar, ptr %ctx, ptr %ctx2) #0 {
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%1 = tail call i64 @llvm.bpf.load.byte(ptr %ctx, i64 123) #2
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%2 = add i64 %1, %foo
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%3 = load volatile i64, ptr %bar, align 8
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%4 = add i64 %2, %3
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%5 = tail call i64 @llvm.bpf.load.byte(ptr %ctx2, i64 %foo) #2
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%6 = add i64 %4, %5
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%7 = load volatile i64, ptr %bar, align 8
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%8 = add i64 %6, %7
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%9 = trunc i64 %8 to i32
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ret i32 %9
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; CHECK-LABEL: ld_b:
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; CHECK-EL: r0 = *(u8 *)skb[123]
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; CHECK-EL: r0 = *(u8 *)skb[r
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; CHECK-EB: r0 = *(u8 *)skb[123]
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; CHECK-EB: r0 = *(u8 *)skb[r
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}
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declare i64 @llvm.bpf.load.byte(ptr, i64) #1
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; Function Attrs: nounwind uwtable
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define i32 @ld_h(ptr %ctx, ptr %ctx2, i32 %foo) #0 {
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%1 = tail call i64 @llvm.bpf.load.half(ptr %ctx, i64 123) #2
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%2 = sext i32 %foo to i64
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%3 = tail call i64 @llvm.bpf.load.half(ptr %ctx2, i64 %2) #2
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%4 = add i64 %3, %1
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%5 = trunc i64 %4 to i32
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ret i32 %5
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; CHECK-LABEL: ld_h:
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; CHECK-EL: r0 = *(u16 *)skb[r
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; CHECK-EL: r0 = *(u16 *)skb[123]
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; CHECK-EB: r0 = *(u16 *)skb[r
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; CHECK-EB: r0 = *(u16 *)skb[123]
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}
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declare i64 @llvm.bpf.load.half(ptr, i64) #1
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; Function Attrs: nounwind uwtable
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define i32 @ld_w(ptr %ctx, ptr %ctx2, i32 %foo) #0 {
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%1 = tail call i64 @llvm.bpf.load.word(ptr %ctx, i64 123) #2
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%2 = sext i32 %foo to i64
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%3 = tail call i64 @llvm.bpf.load.word(ptr %ctx2, i64 %2) #2
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%4 = add i64 %3, %1
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%5 = trunc i64 %4 to i32
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ret i32 %5
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; CHECK-LABEL: ld_w:
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; CHECK-EL: r0 = *(u32 *)skb[r
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; CHECK-EL: r0 = *(u32 *)skb[123]
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; CHECK-EB: r0 = *(u32 *)skb[r
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; CHECK-EB: r0 = *(u32 *)skb[123]
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}
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declare i64 @llvm.bpf.load.word(ptr, i64) #1
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define i32 @ld_pseudo() #0 {
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entry:
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%call = tail call i64 @llvm.bpf.pseudo(i64 2, i64 3)
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tail call void inttoptr (i64 4 to ptr)(i64 %call, i32 4) #2
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ret i32 0
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; CHECK-LABEL: ld_pseudo:
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; CHECK-EL: ld_pseudo r1, 2, 3
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; CHECK-EB: ld_pseudo r1, 2, 3
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}
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declare i64 @llvm.bpf.pseudo(i64, i64) #2
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define i32 @bswap(i64 %a, i64 %b, i64 %c) #0 {
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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%conv = trunc i64 %b to i32
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%1 = tail call i32 @llvm.bswap.i32(i32 %conv)
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%conv1 = zext i32 %1 to i64
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%add = add i64 %conv1, %0
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%conv2 = trunc i64 %c to i16
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%2 = tail call i16 @llvm.bswap.i16(i16 %conv2)
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%conv3 = zext i16 %2 to i64
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%add4 = add i64 %add, %conv3
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%conv5 = trunc i64 %add4 to i32
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ret i32 %conv5
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; CHECK-LABEL: bswap:
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; CHECK-EL: r1 = be64 r1
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; CHECK-EL: r0 = be32 r0
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; CHECK-EL: r0 += r1
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; CHECK-EL: r3 = be16 r3
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; CHECK-EL: r0 += r3
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; CHECK-EB: r1 = le64 r1
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; CHECK-EB: r0 = le32 r0
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; CHECK-EB: r0 += r1
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; CHECK-EB: r3 = le16 r3
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; CHECK-EB: r0 += r3
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}
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declare i64 @llvm.bswap.i64(i64) #1
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declare i32 @llvm.bswap.i32(i32) #1
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declare i16 @llvm.bswap.i16(i16) #1
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