70b8b738c5
Normally, generic processor does not have any SubtargetFeature. And it can just generate most basic instructions which have no Predicates to guard. But it needs to enbale predicate for the btsti16 instruction as one of the most basic instructions. Or the generic processor can't finish codegen process. So Add FeatureBTST16 SubtargetFeature to generic ProcessorModel.
75 lines
2.6 KiB
LLVM
75 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
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define float @selectRR_eq_float(i1 %x, float %n, float %m) {
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; CHECK-LABEL: selectRR_eq_float:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: btsti16 a0, 0
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; CHECK-NEXT: bt32 .LBB0_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: fmovs vr1, vr0
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; CHECK-NEXT: .LBB0_2: # %entry
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; CHECK-NEXT: fmovs vr0, vr1
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; CHECK-NEXT: rts16
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;
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; CHECK-DF3-LABEL: selectRR_eq_float:
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; CHECK-DF3: # %bb.0: # %entry
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; CHECK-DF3-NEXT: btsti16 a0, 0
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; CHECK-DF3-NEXT: fsel.32 vr0, vr1, vr0
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; CHECK-DF3-NEXT: rts16
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;
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; GENERIC-LABEL: selectRR_eq_float:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: .cfi_def_cfa_offset 0
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; GENERIC-NEXT: subi16 sp, sp, 4
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; GENERIC-NEXT: .cfi_def_cfa_offset 4
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; GENERIC-NEXT: btsti16 a0, 0
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; GENERIC-NEXT: bt16 .LBB0_2
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; GENERIC-NEXT: # %bb.1: # %entry
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; GENERIC-NEXT: fmovs vr1, vr0
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; GENERIC-NEXT: .LBB0_2: # %entry
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; GENERIC-NEXT: fmovs vr0, vr1
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; GENERIC-NEXT: addi16 sp, sp, 4
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; GENERIC-NEXT: rts16
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entry:
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%ret = select i1 %x, float %m, float %n
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ret float %ret
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}
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define double @selectRR_eq_double(i1 %x, double %n, double %m) {
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; CHECK-LABEL: selectRR_eq_double:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: btsti16 a0, 0
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; CHECK-NEXT: bt32 .LBB1_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: fmovd vr1, vr0
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; CHECK-NEXT: .LBB1_2: # %entry
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; CHECK-NEXT: fmovd vr0, vr1
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; CHECK-NEXT: rts16
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;
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; CHECK-DF3-LABEL: selectRR_eq_double:
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; CHECK-DF3: # %bb.0: # %entry
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; CHECK-DF3-NEXT: btsti16 a0, 0
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; CHECK-DF3-NEXT: fsel.64 vr0, vr1, vr0
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; CHECK-DF3-NEXT: rts16
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;
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; GENERIC-LABEL: selectRR_eq_double:
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; GENERIC: # %bb.0: # %entry
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; GENERIC-NEXT: .cfi_def_cfa_offset 0
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; GENERIC-NEXT: subi16 sp, sp, 4
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; GENERIC-NEXT: .cfi_def_cfa_offset 4
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; GENERIC-NEXT: btsti16 a0, 0
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; GENERIC-NEXT: bt16 .LBB1_2
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; GENERIC-NEXT: # %bb.1: # %entry
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; GENERIC-NEXT: fmovd vr1, vr0
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; GENERIC-NEXT: .LBB1_2: # %entry
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; GENERIC-NEXT: fmovd vr0, vr1
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; GENERIC-NEXT: addi16 sp, sp, 4
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; GENERIC-NEXT: rts16
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entry:
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%ret = select i1 %x, double %m, double %n
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ret double %ret
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}
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