369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
133 lines
3.5 KiB
LLVM
133 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s | FileCheck %s
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; RUN: %if ptxas %{ llc < %s | %ptxas-verify %}
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target triple = "nvptx64-nvidia-cuda"
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define i32 @flo_1(i32 %a) {
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; CHECK-LABEL: flo_1(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [flo_1_param_0];
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; CHECK-NEXT: bfind.s32 %r2, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.s.i32(i32 %a, i1 false)
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ret i32 %r
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}
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define i32 @flo_2(i32 %a) {
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; CHECK-LABEL: flo_2(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [flo_2_param_0];
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; CHECK-NEXT: bfind.shiftamt.s32 %r2, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.s.i32(i32 %a, i1 true)
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ret i32 %r
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}
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define i32 @flo_3(i32 %a) {
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; CHECK-LABEL: flo_3(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [flo_3_param_0];
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; CHECK-NEXT: bfind.u32 %r2, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.u.i32(i32 %a, i1 false)
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ret i32 %r
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}
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define i32 @flo_4(i32 %a) {
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; CHECK-LABEL: flo_4(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<3>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [flo_4_param_0];
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; CHECK-NEXT: bfind.shiftamt.u32 %r2, %r1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.u.i32(i32 %a, i1 true)
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ret i32 %r
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}
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define i32 @flo_5(i64 %a) {
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; CHECK-LABEL: flo_5(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .b64 %rd<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [flo_5_param_0];
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; CHECK-NEXT: bfind.s64 %r1, %rd1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.s.i64(i64 %a, i1 false)
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ret i32 %r
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}
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define i32 @flo_6(i64 %a) {
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; CHECK-LABEL: flo_6(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .b64 %rd<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [flo_6_param_0];
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; CHECK-NEXT: bfind.shiftamt.s64 %r1, %rd1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.s.i64(i64 %a, i1 true)
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ret i32 %r
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}
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define i32 @flo_7(i64 %a) {
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; CHECK-LABEL: flo_7(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .b64 %rd<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [flo_7_param_0];
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; CHECK-NEXT: bfind.u64 %r1, %rd1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.u.i64(i64 %a, i1 false)
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ret i32 %r
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}
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define i32 @flo_8(i64 %a) {
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; CHECK-LABEL: flo_8(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .b64 %rd<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [flo_8_param_0];
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; CHECK-NEXT: bfind.shiftamt.u64 %r1, %rd1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%r = call i32 @llvm.nvvm.flo.u.i64(i64 %a, i1 true)
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ret i32 %r
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}
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declare i32 @llvm.nvvm.flo.s.i32(i32, i1)
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declare i32 @llvm.nvvm.flo.u.i32(i32, i1)
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declare i32 @llvm.nvvm.flo.s.i64(i64, i1)
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declare i32 @llvm.nvvm.flo.u.i64(i64, i1)
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