d494eb0fa3
When assigning numbers to registers, skip any with neither uses nor defs. This is will not have any impact at all on the final SASS but it makes for slightly more readable PTX. This change should also ensure that future minor changes are less likely to cause noisy diffs in register numbering.
40 lines
1.4 KiB
LLVM
40 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -march=nvptx64 --debug-counter=dagcombine=0 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -march=nvptx64 --debug-counter=dagcombine=0 | %ptxas-verify %}
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; REQUIRES: asserts
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; asserts are required for --debug-counter=dagcombine=0 to have the intended
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; effect of disabling DAG combines, which exposes the bug. When combines are
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; enabled the bug does not occur.
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%struct.1float = type <{ [1 x float] }>
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declare i32 @callee(%struct.1float %a)
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define i32 @test(%struct.1float alignstack(32) %data) {
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; CHECK-LABEL: test(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<6>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [test_param_0];
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; CHECK-NEXT: { // callseq 0, 0
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; CHECK-NEXT: .param .align 1 .b8 param0[4];
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; CHECK-NEXT: .param .b32 retval0;
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; CHECK-NEXT: st.param.b8 [param0], %r1;
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; CHECK-NEXT: shr.u32 %r2, %r1, 8;
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; CHECK-NEXT: st.param.b8 [param0+1], %r2;
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; CHECK-NEXT: shr.u32 %r3, %r1, 16;
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; CHECK-NEXT: st.param.b8 [param0+2], %r3;
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; CHECK-NEXT: shr.u32 %r4, %r3, 8;
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; CHECK-NEXT: st.param.b8 [param0+3], %r4;
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; CHECK-NEXT: call.uni (retval0), callee, (param0);
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; CHECK-NEXT: ld.param.b32 %r5, [retval0];
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; CHECK-NEXT: } // callseq 0
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; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
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; CHECK-NEXT: ret;
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%1 = call i32 @callee(%struct.1float %data)
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ret i32 %1
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}
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