369891b674
In most cases, the type information attached to load and store instructions is meaningless and inconsistently applied. We can usually use ".b" loads and avoid the complexity of trying to assign the correct type. The one expectation is sign-extending load, which will continue to use ".s" to ensure the sign extension into a larger register is done correctly.
32 lines
1.1 KiB
LLVM
32 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
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target triple = "nvptx-unknown-cuda"
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declare void @bar(<4 x i32>)
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; CHECK-LABEL: .func foo(
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; CHECK-DAG: ld.param.v4.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [foo_param_0];
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; CHECK: .param .align 16 .b8 param0[16];
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; CHECK-DAG: st.param.v4.b32 [param0], {[[E0]], [[E1]], [[E2]], [[E3]]};
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; CHECK: call.uni
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; CHECK: ret;
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define void @foo(<4 x i32> %a) {
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tail call void @bar(<4 x i32> %a)
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ret void
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}
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; CHECK-LABEL: .func foo3(
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; CHECK-DAG: ld.param.v2.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]]}, [foo3_param_0];
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; CHECK-DAG: ld.param.b32 [[E2:%r[0-9]+]], [foo3_param_0+8];
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; CHECK: .param .align 16 .b8 param0[16];
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; CHECK-DAG: st.param.v2.b32 [param0], {[[E0]], [[E1]]};
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; CHECK-DAG: st.param.b32 [param0+8], [[E2]];
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; CHECK: call.uni
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; CHECK: ret;
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declare void @bar3(<3 x i32>)
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define void @foo3(<3 x i32> %a) {
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tail call void @bar3(<3 x i32> %a)
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ret void
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}
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