aa91d90cb0
This preserves the semantis of fneg and matches what we do in LegalizeDAG. I kept the legal FSUB check to force unrolling for some targets that don't have FSUB but have XOR. On Aarch64, using xor broke some tests that expected to see a (v1f64 (fma (insertvector_elt (f64 (fneg (extractvectorelt X)))))) pattern.
38 lines
1.1 KiB
LLVM
38 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mattr=+altivec -mattr=+vsx | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s \
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; RUN: -check-prefix=CHECK-NOVSX
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define void @test_float(ptr %A) {
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; CHECK-LABEL: test_float
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; CHECK-NOVSX-LABEL: test_float
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%tmp2 = load <4 x float>, ptr %A
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%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
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store <4 x float> %tmp3, ptr %A
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ret void
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; CHECK: xvnegsp
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; CHECK: blr
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; CHECK-NOVSX: vxor
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; CHECK-NOVSX: blr
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}
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define void @test_double(ptr %A) {
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; CHECK-LABEL: test_double
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; CHECK-NOVSX-LABEL: test_double
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%tmp2 = load <2 x double>, ptr %A
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%tmp3 = fsub <2 x double> < double -0.000000e+00, double -0.000000e+00 >, %tmp2
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store <2 x double> %tmp3, ptr %A
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ret void
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; CHECK: xvnegdp
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; CHECK: blr
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; CHECK-NOVSX: fneg
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; CHECK-NOVSX: fneg
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; CHECK-NOVSX: blr
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}
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