b87dc35669
After the work in a538d1f13a13 5351878ba196 372240dfe3d5, and subsequently cleanup of all the in-tree targets, we can now delete the support for positional operand matching! This removes three options which could previously be set in a Target's "InstrInfo" tablegen definition: - useDeprecatedPositionallyEncodedOperands - decodePositionallyEncodedOperands - noNamedPositionallyEncodedOperands (Also announced at https://discourse.llvm.org/t/tablegen-deleting-deprecated-positional-instruction-operand-matching-support/68524) Differential Revision: https://reviews.llvm.org/D144210
33 lines
777 B
TableGen
33 lines
777 B
TableGen
// RUN: not llvm-tblgen -gen-emitter -I %p/../../include %s 2>&1 | FileCheck %s --implicit-check-not=error:
|
|
|
|
// Check that we emit reasonable diagnostics when fields do not have
|
|
// corresponding operands.
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
def ArchInstrInfo : InstrInfo { }
|
|
|
|
def Arch : Target {
|
|
let InstructionSet = ArchInstrInfo;
|
|
}
|
|
|
|
def Reg : Register<"reg">;
|
|
|
|
def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
|
|
|
|
// CHECK: error: No operand named rd in record foo
|
|
// CHECK: error: No operand named rs in record foo
|
|
// CHECK: note: Dumping record for previous error:
|
|
def foo : Instruction {
|
|
bits<3> rd;
|
|
bits<3> rs;
|
|
|
|
bits<8> Inst;
|
|
let Inst{1-0} = 0;
|
|
let Inst{4-2} = rd;
|
|
let Inst{7-5} = rs;
|
|
|
|
let OutOperandList = (outs Regs:$xd);
|
|
let InOperandList = (ins);
|
|
}
|