b791a51730
Forming a `ReadAdvance` with an entry in the `ValidWrites` list that is not used by any instruction results in the entire `ReadAdvance` to be ignored by the scheduler due to an invalid entry. The `SchedRW` collection code only picks up `SchedWrites` that are reachable from `Instructions`, `InstRW`, `ItinRW` and `SchedAlias`, leaving the unreachable ones with an invalid entry (0) in `SubtargetEmitter::GenSchedClassTables` when going through the list of `ReadAdvances`
30 lines
766 B
TableGen
30 lines
766 B
TableGen
// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
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// Make sure we don't form ReadAdvances with ValidWrites entries that are not
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// associated with any instructions.
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include "llvm/Target/Target.td"
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def TargetX : Target;
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def WriteX : SchedWrite;
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def WriteY : SchedWrite;
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def ReadX : SchedRead;
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def InstX : Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins);
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let SchedRW = [WriteX, ReadX];
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}
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def SchedModelX: SchedMachineModel {
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let CompleteModel = 0;
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}
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let SchedModel = SchedModelX in {
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def : ReadAdvance<ReadX, 1, [WriteX, WriteY]>;
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// CHECK: error: ReadAdvance referencing a ValidWrite that is not used by any instruction (WriteY)
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}
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def ProcessorX: ProcessorModel<"ProcessorX", SchedModelX, []>;
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