eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
28 lines
805 B
LLVM
28 lines
805 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -S -passes=indvars < %s | FileCheck %s
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target datalayout = "n8:16:32:64"
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; Just make sure this doesn't crash.
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; SCEVExpander produces a degenerate phi node for the widened IV here,
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; where the "increment" instruction folds to a poison value.
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define i32 @main() {
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; CHECK-LABEL: define i32 @main() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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%div = sdiv i32 1, 0
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%trunc = trunc i32 %div to i16
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br label %loop
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loop:
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%phi = phi i16 [ 0, %entry ], [ %or, %loop ]
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%or = or disjoint i16 %phi, %trunc
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%phi.ext = sext i16 %phi to i64
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%add.ptr = getelementptr i8, ptr null, i64 %phi.ext
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br label %loop
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}
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