9ef829097b
The bug is that `IsAndVariant` is used to assume which arm in the
select the output `SelInner` should be placed but match the inner
select condition with `m_c_LogicalOp`. With fully simplified ops, this
works fine, but its possible if the select condition is not
simplified, for it match both `LogicalAnd` and `LogicalOr` i.e `select
true, true, false`.
In PR71330 for example, the issue occurs in the following IR:
```
define i32 @bad() {
%..i.i = select i1 false, i32 0, i32 3
%brmerge = select i1 true, i1 true, i1 false
%not.cmp.i.i.not = xor i1 true, true
%.mux = zext i1 %not.cmp.i.i.not to i32
%retval.0.i.i = select i1 %brmerge, i32 %.mux, i32 %..i.i
ret i32 %retval.0.i.i
}
```
When simplifying:
```
%retval.0.i.i = select i1 %brmerge, i32 %.mux, i32 %..i.i
```
We end up matching `%brmerge` as `LogicalAnd` for `IsAndVariant`, but
the inner select (`%..i.i`) condition which is `false` with
`LogicalOr`.
Closes #71489
77 lines
3.1 KiB
LLVM
77 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -passes=instcombine -S < %s | FileCheck %s
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define void @pr71330(i32 %conv, i1 %tobool19.not4, i16 %lb) {
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; CHECK-LABEL: define void @pr71330(
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; CHECK-SAME: i32 [[CONV:%.*]], i1 [[TOBOOL19_NOT4:%.*]], i16 [[LB:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND7_PREHEADER:%.*]]
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; CHECK: for.cond7.preheader:
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; CHECK-NEXT: br i1 [[TOBOOL19_NOT4]], label [[FOR_COND7_PREHEADER_SPLIT_US:%.*]], label [[FOR_COND7:%.*]]
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; CHECK: for.cond7.preheader.split.us:
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; CHECK-NEXT: br i1 true, label [[FOR_COND7_PREHEADER_SPLIT_US_SPLIT:%.*]], label [[FOR_COND7_US_US:%.*]]
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; CHECK: for.cond7.us.us:
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; CHECK-NEXT: br i1 poison, label [[FOR_COND7_US_US]], label [[FOR_END25:%.*]]
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; CHECK: for.cond7.preheader.split.us.split:
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; CHECK-NEXT: ret void
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; CHECK: for.cond7:
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; CHECK-NEXT: [[CMP12:%.*]] = icmp slt i32 [[CONV]], 0
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; CHECK-NEXT: br i1 [[CMP12]], label [[FOR_BODY14:%.*]], label [[FOR_END25]]
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; CHECK: for.body14:
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; CHECK-NEXT: ret void
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; CHECK: for.end25:
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; CHECK-NEXT: br i1 false, label [[FOR_COND7_PREHEADER]], label [[FOR_END36:%.*]]
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; CHECK: for.end36:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.cond7.preheader
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for.cond7.preheader: ; preds = %for.end25, %entry
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%storemerge33 = phi i32 [ -3, %entry ], [ 0, %for.end25 ]
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%sm8 = and i32 %storemerge33, 1
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%add = add i32 %storemerge33, 8
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%cmp.i.i.not = icmp eq i32 %sm8, 0
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%cmp3.i.i = icmp eq i32 %add, 0
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%and7.i.i = and i32 %storemerge33, 1
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%cmp8.i.i = icmp eq i32 %and7.i.i, 0
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%tobool.not.i.i = icmp eq i32 %add, 0
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%..i.i = select i1 %tobool.not.i.i, i32 1, i32 3
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br i1 %tobool19.not4, label %for.cond7.preheader.split.us, label %for.cond7
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for.cond7.preheader.split.us: ; preds = %for.cond7.preheader
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br i1 %cmp.i.i.not, label %for.cond7.us.us, label %for.cond7.preheader.split.us.split
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for.cond7.us.us: ; preds = %for.cond7.us.us, %for.cond7.preheader.split.us
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%spec.select = select i1 %cmp8.i.i, i32 1, i32 %..i.i
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%retval.0.i.i.us.us = select i1 %cmp3.i.i, i32 0, i32 %spec.select
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%add9.us.us = add i32 %retval.0.i.i.us.us, %conv
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%conv10.us.us = sext i32 %add9.us.us to i64
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%cmp12.us.us = icmp slt i64 %conv10.us.us, 0
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br i1 %cmp12.us.us, label %for.cond7.us.us, label %for.end25
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for.cond7.preheader.split.us.split: ; preds = %for.cond7.preheader.split.us
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ret void
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for.cond7: ; preds = %for.cond7.preheader
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%cmp.i.i.not.not = xor i1 %cmp.i.i.not, true
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%brmerge = select i1 %cmp.i.i.not.not, i1 true, i1 %cmp3.i.i
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%spec.select34 = select i1 %cmp8.i.i, i32 1, i32 %..i.i
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%retval.0.i.i = select i1 %brmerge, i32 0, i32 %spec.select34
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%add9 = add i32 %retval.0.i.i, %conv
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%conv10 = sext i32 %add9 to i64
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%cmp12 = icmp slt i64 %conv10, 0
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br i1 %cmp12, label %for.body14, label %for.end25
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for.body14: ; preds = %for.cond7
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ret void
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for.end25: ; preds = %for.cond7, %for.cond7.us.us
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%conv35 = zext i16 %lb to i32
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%cmp = icmp slt i32 %conv35, 0
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br i1 %cmp, label %for.cond7.preheader, label %for.end36
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for.end36: ; preds = %for.end25
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ret void
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}
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