0d38f21e4a
This extends the work from 7755c26 to all of the different backend taken count kinds that we print for the scev analysis printer. As before, the goal is to cut down on confusion as i4 -1 is a very different (unsigned) value from i32 -1.
76 lines
3.3 KiB
LLVM
76 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt < %s -passes='print<scalar-evolution>,simple-loop-unswitch<no-nontrivial>,print<scalar-evolution>' -disable-output 2>&1 | FileCheck -check-prefix CHECK-SCEV %s
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; RUN: opt < %s -passes='function(loop-deletion,simple-loop-unswitch<no-nontrivial>),verify<scalar-evolution>' -S | FileCheck -check-prefix CHECK-IR %s
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; These tests used to hit an assertion failure in llvm::ScalarEvolution::BackedgeTakenInfo::getExact:
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; "We should only have known counts for exiting blocks that dominate latch!"' failed.
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;
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; Verify that we no longer hit that assert, while we expect to have forgotten SCEV for the outer loop.
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; Also added checks to show and verify the IR transformation.
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; Before the unswitch:
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;
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; CHECK-SCEV: Classifying expressions for: @f4
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; CHECK-SCEV-NEXT: %j.0 = phi i16 [ 0, %entry ], [ %0, %sw.bb2 ]
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; CHECK-SCEV-NEXT: --> {0,+,1}<nuw><nsw><%lbl1> U: [0,3) S: [0,3) Exits: 2 LoopDispositions: { %lbl1: Computable, %lbl2: Invariant }
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; CHECK-SCEV-NEXT: %0 = add i16 %j.0, 1
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; CHECK-SCEV-NEXT: --> {1,+,1}<nuw><nsw><%lbl1> U: [1,4) S: [1,4) Exits: 3 LoopDispositions: { %lbl1: Computable, %lbl2: Invariant }
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; CHECK-SCEV-DAG: Loop %lbl2: Unpredictable backedge-taken count.
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; CHECK-SCEV-DAG: Loop %lbl1: backedge-taken count is i16 2
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;
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; After the unswitch:
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;
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; CHECK-SCEV: Classifying expressions for: @f4
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; CHECK-SCEV-NEXT: %j.0 = phi i16 [ 0, %entry ], [ %0, %sw.bb2 ]
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; CHECK-SCEV-NEXT: --> {0,+,1}<nuw><nsw><%lbl1> U: [0,-32768) S: [0,-32768) Exits: <<Unknown>> LoopDispositions: { %lbl1: Computable }
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; CHECK-SCEV-NEXT: %0 = add i16 %j.0, 1
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; CHECK-SCEV-NEXT: --> {1,+,1}<nuw><nsw><%lbl1> U: [1,-32768) S: [1,-32768) Exits: <<Unknown>> LoopDispositions: { %lbl1: Computable }
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; CHECK-SCEV-DAG: Loop %lbl1: Unpredictable backedge-taken count.
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; CHECK-SCEV-DAG: Loop %lbl2: <multiple exits> Unpredictable backedge-taken count.
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define i16 @f4() {
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; CHECK-IR-LABEL: define i16 @f4() {
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; CHECK-IR-NEXT: entry:
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; CHECK-IR-NEXT: br label [[LBL1:%.*]]
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; CHECK-IR: lbl1:
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; CHECK-IR-NEXT: [[J_0:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[TMP0:%.*]], [[SW_BB2:%.*]] ]
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; CHECK-IR-NEXT: switch i16 [[J_0]], label [[LBL1_SPLIT:%.*]] [
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; CHECK-IR-NEXT: i16 0, label [[SW_BB2]]
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; CHECK-IR-NEXT: i16 1, label [[SW_BB2]]
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; CHECK-IR-NEXT: i16 2, label [[LBL3:%.*]]
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; CHECK-IR-NEXT: ]
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; CHECK-IR: lbl1.split:
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; CHECK-IR-NEXT: br label [[LBL2:%.*]]
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; CHECK-IR: lbl2:
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; CHECK-IR-NEXT: br label [[LBL2]]
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; CHECK-IR: sw.bb2:
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; CHECK-IR-NEXT: [[TMP0]] = add i16 [[J_0]], 1
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; CHECK-IR-NEXT: br label [[LBL1]]
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; CHECK-IR: lbl3:
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; CHECK-IR-NEXT: ret i16 0
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;
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entry:
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br label %lbl1
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lbl1: ; preds = %sw.bb2, %entry
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%j.0 = phi i16 [ 0, %entry ], [ %0, %sw.bb2 ]
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br label %lbl2
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lbl2: ; preds = %lbl2, %lbl1
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switch i16 %j.0, label %lbl2 [
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i16 0, label %sw.bb2
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i16 1, label %sw.bb2
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i16 2, label %lbl3
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]
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sw.bb2: ; preds = %lbl2, %lbl2
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%0 = add i16 %j.0, 1
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br label %lbl1
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lbl3: ; preds = %lbl2
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ret i16 0
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}
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