20d8398825
Whole wave functions are functions that will run with a full EXEC mask. They will not be invoked directly, but instead will be launched by way of a new intrinsic, `llvm.amdgcn.call.whole.wave` (to be added in a future patch). These functions are meant as an alternative to the `llvm.amdgcn.init.whole.wave` or `llvm.amdgcn.strict.wwm` intrinsics. Whole wave functions will set EXEC to -1 in the prologue and restore the original value of EXEC in the epilogue. They must have a special first argument, `i1 %active`, that is going to be mapped to EXEC. They may have either the default calling convention or amdgpu_gfx. The inactive lanes need to be preserved for all registers used, active lanes only for the CSRs. At the IR level, arguments to a whole wave function (other than `%active`) contain poison in their inactive lanes. Likewise, the return value for the inactive lanes is poison. This patch contains the following work: * 2 new pseudos, SI_SETUP_WHOLE_WAVE_FUNC and SI_WHOLE_WAVE_FUNC_RETURN used for managing the EXEC mask. SI_SETUP_WHOLE_WAVE_FUNC will return a SReg_1 representing `%active`, which needs to be passed into SI_WHOLE_WAVE_FUNC_RETURN. * SelectionDAG support for generating these 2 new pseudos and the special handling of %active. Since the return may be in a different basic block, it's difficult to add the virtual reg for %active to SI_WHOLE_WAVE_FUNC_RETURN, so we initially generate an IMPLICIT_DEF which is later replaced via a custom inserter. * Expansion of the 2 pseudos during prolog/epilog insertion. PEI also marks any used VGPRs as WWM registers, which are then spilled and restored with the usual logic. Future patches will include the `llvm.amdgcn.call.whole.wave` intrinsic and a lot of optimization work (especially in order to reduce spills around function calls). --------- Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com> Co-authored-by: Shilei Tian <i@tianshilei.me>
253 lines
7.9 KiB
LLVM
253 lines
7.9 KiB
LLVM
; RUN: not llvm-as < %s 2>&1 | FileCheck %s
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target datalayout = "A5"
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; CHECK: Calling convention requires void return type
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; CHECK-NEXT: ptr @nonvoid_cc_amdgpu_kernel
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define amdgpu_kernel i32 @nonvoid_cc_amdgpu_kernel() {
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ret i32 0
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_kernel
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define amdgpu_kernel void @varargs_amdgpu_kernel(...) {
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ret void
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}
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; CHECK: Calling convention does not allow sret
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; CHECK-NEXT: ptr @sret_cc_amdgpu_kernel_as0
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define amdgpu_kernel void @sret_cc_amdgpu_kernel_as0(ptr sret(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention does not allow sret
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; CHECK-NEXT: ptr @sret_cc_amdgpu_kernel
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define amdgpu_kernel void @sret_cc_amdgpu_kernel(ptr addrspace(5) sret(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_vs
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define amdgpu_vs void @varargs_amdgpu_vs(...) {
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ret void
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_gs
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define amdgpu_gs void @varargs_amdgpu_gs(...) {
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ret void
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_ps
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define amdgpu_ps void @varargs_amdgpu_ps(...) {
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ret void
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_cs
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define amdgpu_cs void @varargs_amdgpu_cs(...) {
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ret void
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}
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; CHECK: Calling convention requires void return type
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; CHECK-NEXT: ptr @nonvoid_cc_spir_kernel
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define spir_kernel i32 @nonvoid_cc_spir_kernel() {
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ret i32 0
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_spir_kernel
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define spir_kernel void @varargs_spir_kernel(...) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_kernel
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define amdgpu_kernel void @byval_cc_amdgpu_kernel(ptr addrspace(5) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_as1_cc_amdgpu_kernel
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define amdgpu_kernel void @byval_as1_cc_amdgpu_kernel(ptr addrspace(1) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_as0_cc_amdgpu_kernel
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define amdgpu_kernel void @byval_as0_cc_amdgpu_kernel(ptr byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_vs
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define amdgpu_vs void @byval_cc_amdgpu_vs(ptr addrspace(5) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_hs
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define amdgpu_hs void @byval_cc_amdgpu_hs(ptr addrspace(5) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_gs
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define amdgpu_gs void @byval_cc_amdgpu_gs(ptr addrspace(5) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_ps
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define amdgpu_ps void @byval_cc_amdgpu_ps(ptr addrspace(5) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_cs
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define amdgpu_cs void @byval_cc_amdgpu_cs(ptr addrspace(5) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows preallocated
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; CHECK-NEXT: ptr @preallocated_as0_cc_amdgpu_kernel
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define amdgpu_kernel void @preallocated_as0_cc_amdgpu_kernel(ptr preallocated(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows inalloca
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; CHECK-NEXT: ptr @inalloca_as0_cc_amdgpu_kernel
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define amdgpu_kernel void @inalloca_as0_cc_amdgpu_kernel(ptr inalloca(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows stack byref
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; CHECK-NEXT: ptr @byref_as5_cc_amdgpu_kernel
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define amdgpu_kernel void @byref_as5_cc_amdgpu_kernel(ptr addrspace(5) byref(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention requires void return type
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; CHECK-NEXT: ptr @nonvoid_cc_amdgpu_cs_chain
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define amdgpu_cs_chain i32 @nonvoid_cc_amdgpu_cs_chain() {
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ret i32 0
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_cs_chain
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define amdgpu_cs_chain void @varargs_amdgpu_cs_chain(...) {
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ret void
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}
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; CHECK: Calling convention does not allow sret
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; CHECK-NEXT: ptr @sret_cc_amdgpu_cs_chain_as0
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define amdgpu_cs_chain void @sret_cc_amdgpu_cs_chain_as0(ptr sret(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_cs_chain
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define amdgpu_cs_chain void @byval_cc_amdgpu_cs_chain(ptr addrspace(1) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows stack byref
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; CHECK-NEXT: ptr @byref_cc_amdgpu_cs_chain
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define amdgpu_cs_chain void @byref_cc_amdgpu_cs_chain(ptr addrspace(5) byref(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows preallocated
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; CHECK-NEXT: ptr @preallocated_cc_amdgpu_cs_chain
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define amdgpu_cs_chain void @preallocated_cc_amdgpu_cs_chain(ptr preallocated(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows inalloca
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; CHECK-NEXT: ptr @inalloca_cc_amdgpu_cs_chain
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define amdgpu_cs_chain void @inalloca_cc_amdgpu_cs_chain(ptr inalloca(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention requires void return type
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; CHECK-NEXT: ptr @nonvoid_cc_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve i32 @nonvoid_cc_amdgpu_cs_chain_preserve() {
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ret i32 0
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}
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; CHECK: Calling convention does not support varargs or perfect forwarding!
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; CHECK-NEXT: ptr @varargs_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve void @varargs_amdgpu_cs_chain_preserve(...) {
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ret void
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}
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; CHECK: Calling convention does not allow sret
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; CHECK-NEXT: ptr @sret_cc_amdgpu_cs_chain_preserve_as0
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define amdgpu_cs_chain_preserve void @sret_cc_amdgpu_cs_chain_preserve_as0(ptr sret(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention does not allow sret
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; CHECK-NEXT: ptr @sret_cc_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve void @sret_cc_amdgpu_cs_chain_preserve(ptr addrspace(5) sret(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows byval
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; CHECK-NEXT: ptr @byval_cc_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve void @byval_cc_amdgpu_cs_chain_preserve(ptr addrspace(1) byval(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows stack byref
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; CHECK-NEXT: ptr @byref_cc_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve void @byref_cc_amdgpu_cs_chain_preserve(ptr addrspace(5) byref(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows preallocated
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; CHECK-NEXT: ptr @preallocated_cc_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve void @preallocated_cc_amdgpu_cs_chain_preserve(ptr preallocated(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention disallows inalloca
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; CHECK-NEXT: ptr @inalloca_cc_amdgpu_cs_chain_preserve
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define amdgpu_cs_chain_preserve void @inalloca_cc_amdgpu_cs_chain_preserve(ptr inalloca(i32) %ptr) {
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ret void
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}
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; CHECK: Calling convention requires first argument to be i1
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; CHECK-NEXT: ptr @whole_wave_no_args
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define amdgpu_gfx_whole_wave void @whole_wave_no_args() {
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ret void
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}
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; CHECK: Calling convention requires first argument to be i1
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; CHECK-NEXT: ptr @whole_wave_must_have_i1_active
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define amdgpu_gfx_whole_wave void @whole_wave_must_have_i1_active(i32 %x) {
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ret void
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}
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; CHECK: Calling convention requires first argument to not be inreg
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; CHECK-NEXT: ptr @whole_wave_i1_active_inreg
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define amdgpu_gfx_whole_wave void @whole_wave_i1_active_inreg(i1 inreg %active) {
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ret void
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}
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; CHECK: Calling convention does not support varargs
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; CHECK-NEXT: ptr @whole_wave_varargs
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define amdgpu_gfx_whole_wave void @whole_wave_varargs(i1 %active, i32 %x, ...) {
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ret void
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}
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declare amdgpu_gfx_whole_wave void @whole_wave_callee(i1 %active)
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; CHECK: calling convention does not permit calls
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; CHECK-NEXT: call amdgpu_gfx_whole_wave void @whole_wave_callee(i1 true)
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define amdgpu_cs void @cant_call_whole_wave_func() {
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call amdgpu_gfx_whole_wave void @whole_wave_callee(i1 true)
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ret void
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}
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