89b57061f7
This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support. This allows us to ensure that Support doesn't have includes from MC/*. Differential Revision: https://reviews.llvm.org/D111454
132 lines
4.5 KiB
C++
132 lines
4.5 KiB
C++
//===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Target.h"
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#include <cassert>
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#include <memory>
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "TestBase.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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namespace llvm {
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namespace exegesis {
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namespace {
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using testing::AllOf;
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using testing::ElementsAre;
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using testing::Eq;
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using testing::Matcher;
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using testing::Property;
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Matcher<MCOperand> IsImm(int64_t Value) {
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return AllOf(Property(&MCOperand::isImm, Eq(true)),
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Property(&MCOperand::getImm, Eq(Value)));
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}
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Matcher<MCOperand> IsReg(unsigned Reg) {
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return AllOf(Property(&MCOperand::isReg, Eq(true)),
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Property(&MCOperand::getReg, Eq(Reg)));
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}
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Matcher<MCInst> OpcodeIs(unsigned Opcode) {
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return Property(&MCInst::getOpcode, Eq(Opcode));
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}
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Matcher<MCInst> IsLoadLow16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
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const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64;
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const unsigned ORi = IsGPR32 ? Mips::ORi : Mips::ORi64;
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return AllOf(OpcodeIs(ORi),
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ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value)));
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}
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Matcher<MCInst> IsLoadHigh16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
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const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64;
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return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value)));
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}
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Matcher<MCInst> IsShift(unsigned Reg, uint16_t Amount, bool IsGPR32) {
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const unsigned SLL = IsGPR32 ? Mips::SLL : Mips::SLL64_64;
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return AllOf(OpcodeIs(SLL),
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ElementsAre(IsReg(Reg), IsReg(Reg), IsImm(Amount)));
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}
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class MipsTargetTest : public MipsTestBase {
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protected:
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std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
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return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
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Value);
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}
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};
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TEST_F(MipsTargetTest, SetGPR32RegTo16BitValue) {
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const uint16_t Value = 0xFFFFU;
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const unsigned Reg = Mips::T0;
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EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
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ElementsAre(IsLoadLow16BitImm(Reg, Value, true)));
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}
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TEST_F(MipsTargetTest, SetGPR64RegTo16BitValue) {
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const uint16_t Value = 0xFFFFU;
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const unsigned Reg = Mips::T0_64;
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EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
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ElementsAre(IsLoadLow16BitImm(Reg, Value, false)));
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}
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TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) {
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const uint32_t Value0 = 0xFFFF0000UL;
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const unsigned Reg0 = Mips::T0;
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EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
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ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true)));
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const uint32_t Value1 = 0xFFFFFFFFUL;
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const unsigned Reg1 = Mips::T1;
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EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
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ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true),
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IsLoadLow16BitImm(Reg1, 0xFFFFU, true)));
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}
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TEST_F(MipsTargetTest, SetGPR64RegTo32BitValue) {
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const uint32_t Value0 = 0x7FFF0000UL;
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const unsigned Reg0 = Mips::T0_64;
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EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
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ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false)));
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const uint32_t Value1 = 0x7FFFFFFFUL;
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const unsigned Reg1 = Mips::T1_64;
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EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
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ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false),
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IsLoadLow16BitImm(Reg1, 0xFFFFU, false)));
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const uint32_t Value2 = 0xFFFF0000UL;
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const unsigned Reg2 = Mips::T2_64;
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EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)),
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ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false),
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IsShift(Reg2, 16, false)));
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const uint32_t Value3 = 0xFFFFFFFFUL;
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const unsigned Reg3 = Mips::T3_64;
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EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)),
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ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false),
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IsShift(Reg3, 16, false),
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IsLoadLow16BitImm(Reg3, 0xFFFFU, false)));
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}
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TEST_F(MipsTargetTest, DefaultPfmCounters) {
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const std::string Expected = "CYCLES";
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EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,
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Expected);
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EXPECT_EQ(
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State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,
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Expected);
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}
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} // namespace
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} // namespace exegesis
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} // namespace llvm
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