50320504c8
FPSCR and FPEXC will be stored in FPStatusRegs, after GPRCS2 has been saved. - GPRCS1 - GPRCS2 - FPStatusRegs (new) - DPRCS - GPRCS3 - DPRCS2 FPSCR is present on all targets with a VFP, but the FPEXC register is not present on Cortex-M devices, so different amounts of bytes are being pushed onto the stack depending on our target, which would affect alignment for subsequent saves. DPRCS1 will sum up all previous bytes that were saved, and will emit extra instructions to ensure that its alignment is correct. My assumption is that if DPRCS1 is able to correct its alignment to be correct, then all subsequent saves will also have correct alignment. Avoid annotating the saving of FPSCR and FPEXC for functions marked with the interrupt_save_fp attribute, even though this is done as part of frame setup. Since these are status registers, there really is no viable way of annotating this. Since these aren't GPRs or DPRs, they can't be used with .save or .vsave directives. Instead, just record that the intermediate registers r4 and r5 are saved to the stack again. Co-authored-by: Jake Vossen <jake@vossen.dev> Co-authored-by: Alan Phipps <a-phipps@ti.com>
120 lines
4.8 KiB
C++
120 lines
4.8 KiB
C++
//===- ARMTargetFrameLowering.h - Define frame lowering for ARM -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Support/TypeSize.h"
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namespace llvm {
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class ARMSubtarget;
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class CalleeSavedInfo;
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class MachineFunction;
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class ARMFrameLowering : public TargetFrameLowering {
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protected:
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const ARMSubtarget &STI;
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public:
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explicit ARMFrameLowering(const ARMSubtarget &sti);
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool keepFramePointer(const MachineFunction &MF) const;
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bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
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bool isFPReserved(const MachineFunction &MF) const;
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bool requiresAAPCSFrameRecord(const MachineFunction &MF) const;
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bool hasReservedCallFrame(const MachineFunction &MF) const override;
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bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
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StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const override;
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int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg, int SPAdj) const;
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void getCalleeSaves(const MachineFunction &MF,
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BitVector &SavedRegs) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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/// Update the IsRestored flag on LR if it is spilled, based on the return
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/// instructions.
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static void updateLRRestored(MachineFunction &MF);
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void processFunctionBeforeFrameFinalized(
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MachineFunction &MF, RegScavenger *RS = nullptr) const override;
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void adjustForSegmentedStacks(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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/// Returns true if the target will correctly handle shrink wrapping.
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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bool isProfitableForNoCSROpt(const Function &F) const override {
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// The no-CSR optimisation is bad for code size on ARM, because we can save
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// many registers with a single PUSH/POP pair.
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return false;
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}
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bool
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assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI,
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std::vector<CalleeSavedInfo> &CSI) const override;
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const SpillSlot *
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getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
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protected:
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bool hasFPImpl(const MachineFunction &MF) const override;
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private:
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, unsigned StmOpc,
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unsigned StrOpc, bool NoGap,
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function_ref<bool(unsigned)> Func) const;
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void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI, unsigned LdmOpc,
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unsigned LdrOpc, bool isVarArg, bool NoGap,
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function_ref<bool(unsigned)> Func) const;
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void emitFPStatusSaves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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unsigned PushOneOpc) const;
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void emitFPStatusRestores(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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unsigned LdrOpc) const;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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