618 lines
39 KiB
TableGen
618 lines
39 KiB
TableGen
class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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//===----------------------------------------------------------------------===//
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// ARM Processor subtarget features.
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//
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def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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"Cortex-A5 ARM processors", []>;
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def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
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"Cortex-A7 ARM processors", []>;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors", []>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors", []>;
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def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
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"Cortex-A12 ARM processors", []>;
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def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
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"Cortex-A15 ARM processors", []>;
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def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
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"Cortex-A17 ARM processors", []>;
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def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
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"Cortex-A32 ARM processors", []>;
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def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
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"Cortex-A35 ARM processors", []>;
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def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors", []>;
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def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
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"Cortex-A55 ARM processors", []>;
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def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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"Cortex-A57 ARM processors", []>;
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def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
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"Cortex-A72 ARM processors", []>;
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def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
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"Cortex-A73 ARM processors", []>;
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def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
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"Cortex-A75 ARM processors", []>;
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def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
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"Cortex-A76 ARM processors", []>;
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def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
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"Cortex-A77 ARM processors", []>;
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def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78",
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"Cortex-A78 ARM processors", []>;
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def ProcA78AE : SubtargetFeature<"cortex-a78ae", "ARMProcFamily", "CortexA78AE",
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"Cortex-A78AE ARM processors", []>;
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def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C",
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"Cortex-A78C ARM processors", []>;
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def ProcA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
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"CortexA510", "Cortex-A510 ARM processors", []>;
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def ProcA710 : SubtargetFeature<"cortex-a710", "ARMProcFamily",
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"CortexA710", "Cortex-A710 ARM processors", []>;
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def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
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"Cortex-X1 ARM processors", []>;
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def ProcX1C : SubtargetFeature<"cortex-x1c", "ARMProcFamily", "CortexX1C",
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"Cortex-X1C ARM processors", []>;
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def ProcV1 : SubtargetFeature<"neoverse-v1", "ARMProcFamily",
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"NeoverseV1", "Neoverse-V1 ARM processors", []>;
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def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
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"Qualcomm Krait processors", []>;
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def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
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"Qualcomm Kryo processors", []>;
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def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
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"Swift ARM processors", []>;
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def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
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"Samsung Exynos processors",
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[FeatureZCZeroing,
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FeatureUseWideStrideVFP,
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FeatureSplatVFPToNeon,
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FeatureSlowVGETLNi32,
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FeatureSlowVDUP32,
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FeatureSlowFPBrcc,
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FeatureProfUnpredicate,
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FeatureHWDivThumb,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureHasRetAddrStack,
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FeatureFuseLiterals,
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FeatureFuseAES,
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FeatureExpandMLx,
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FeatureCrypto,
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FeatureCRC]>;
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def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
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"Cortex-R4 ARM processors", []>;
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def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
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"Cortex-R5 ARM processors", []>;
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def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
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"Cortex-R7 ARM processors", []>;
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def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
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"Cortex-R52 ARM processors", []>;
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def ProcR52plus : SubtargetFeature<"r52plus", "ARMProcFamily", "CortexR52plus",
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"Cortex-R52plus ARM processors", []>;
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def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
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"Cortex-M3 ARM processors", []>;
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def ProcM55 : SubtargetFeature<"m55", "ARMProcFamily", "CortexM55",
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"Cortex-M55 ARM processors", []>;
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def ProcM7 : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7",
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"Cortex-M7 ARM processors", []>;
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def ProcM85 : SubtargetFeature<"m85", "ARMProcFamily", "CortexM85",
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"Cortex-M85 ARM processors", []>;
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//===----------------------------------------------------------------------===//
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// ARM processors
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//
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// Dummy CPU, used to target architectures
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def : ProcessorModel<"generic", CortexA8Model, []>;
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// FIXME: Several processors below are not using their own scheduler
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// model, but one of similar/previous processor. These should be fixed.
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def : ProcNoItin<"arm8", [ARMv4]>;
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def : ProcNoItin<"arm810", [ARMv4]>;
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def : ProcNoItin<"strongarm", [ARMv4]>;
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def : ProcNoItin<"strongarm110", [ARMv4]>;
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def : ProcNoItin<"strongarm1100", [ARMv4]>;
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def : ProcNoItin<"strongarm1110", [ARMv4]>;
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def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
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def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
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def : ProcNoItin<"arm710t", [ARMv4t]>;
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def : ProcNoItin<"arm720t", [ARMv4t]>;
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def : ProcNoItin<"arm9", [ARMv4t]>;
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def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
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def : ProcNoItin<"arm920", [ARMv4t]>;
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def : ProcNoItin<"arm920t", [ARMv4t]>;
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def : ProcNoItin<"arm922t", [ARMv4t]>;
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def : ProcNoItin<"arm940t", [ARMv4t]>;
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def : ProcNoItin<"ep9312", [ARMv4t]>;
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def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
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def : ProcNoItin<"arm1020t", [ARMv5t]>;
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def : ProcNoItin<"arm9e", [ARMv5te]>;
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def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
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def : ProcNoItin<"arm946e-s", [ARMv5te]>;
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def : ProcNoItin<"arm966e-s", [ARMv5te]>;
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def : ProcNoItin<"arm968e-s", [ARMv5te]>;
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def : ProcNoItin<"arm10e", [ARMv5te]>;
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def : ProcNoItin<"arm1020e", [ARMv5te]>;
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def : ProcNoItin<"arm1022e", [ARMv5te]>;
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def : ProcNoItin<"xscale", [ARMv5te]>;
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def : ProcNoItin<"iwmmxt", [ARMv5te]>;
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def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
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def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
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FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m,
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FeatureHasNoBranchPredictor]>;
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def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m,
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FeatureHasNoBranchPredictor]>;
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def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m,
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FeatureHasNoBranchPredictor]>;
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def : Processor<"sc000", ARMV6Itineraries, [ARMv6m,
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FeatureHasNoBranchPredictor]>;
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def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
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def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
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FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
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def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
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FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
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FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureSlowFPBrcc,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureVMLxForwarding,
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FeatureMP,
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FeatureVFP4]>;
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def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureSlowFPBrcc,
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FeatureHasVMLxHazards,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureVMLxForwarding,
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FeatureMP,
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FeatureVFP4,
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FeatureVirtualization]>;
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def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
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FeatureHasRetAddrStack,
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FeatureNonpipelinedVFP,
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FeatureTrustZone,
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FeatureSlowFPBrcc,
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FeatureHasVMLxHazards,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureVMLxForwarding]>;
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def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureHasVMLxHazards,
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FeatureVMLxForwarding,
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FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureExpandMLx,
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FeaturePreferVMOVSR,
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FeatureMuxedUnits,
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FeatureNEONForFPMovs,
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FeatureCheckVLDnAlign,
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FeatureMP]>;
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def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureVMLxForwarding,
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FeatureVFP4,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization,
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FeatureMP]>;
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def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
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FeatureDontWidenVMOVS,
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FeatureSplatVFPToNeon,
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FeatureHasRetAddrStack,
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FeatureMuxedUnits,
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FeatureTrustZone,
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FeatureVFP4,
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FeatureMP,
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FeatureCheckVLDnAlign,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization]>;
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def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureMP,
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FeatureVMLxForwarding,
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FeatureVFP4,
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FeatureAvoidPartialCPSR,
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FeatureVirtualization]>;
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// FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv
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def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
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FeatureHasRetAddrStack,
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FeatureMuxedUnits,
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FeatureCheckVLDnAlign,
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FeatureVMLxForwarding,
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FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureVFP4,
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FeatureHWDivThumb,
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FeatureHWDivARM]>;
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def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
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FeatureHasRetAddrStack,
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FeatureNEONForFP,
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FeatureVFP4,
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FeatureUseWideStrideVFP,
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FeatureMP,
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FeatureHWDivThumb,
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FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureAvoidMOVsShOp,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureHasVMLxHazards,
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FeatureProfUnpredicate,
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FeaturePrefISHSTBarrier,
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FeatureSlowOddRegister,
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FeatureSlowLoadDSubreg,
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FeatureSlowVGETLNi32,
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FeatureSlowVDUP32,
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FeatureUseMISched,
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FeatureNoPostRASched]>;
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def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
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FeatureHasRetAddrStack,
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FeatureAvoidPartialCPSR]>;
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def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
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FeatureHasRetAddrStack,
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FeatureSlowFPBrcc,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureVFP3_D16,
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FeatureAvoidPartialCPSR]>;
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def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
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FeatureHasRetAddrStack,
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FeatureVFP3_D16,
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FeatureSlowFPBrcc,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureAvoidPartialCPSR]>;
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def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
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FeatureHasRetAddrStack,
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FeatureVFP3_D16,
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FeatureFP16,
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FeatureMP,
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FeatureSlowFPBrcc,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureAvoidPartialCPSR]>;
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def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
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FeatureHasRetAddrStack,
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FeatureVFP3_D16,
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FeatureFP16,
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FeatureMP,
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FeatureSlowFPBrcc,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureAvoidPartialCPSR]>;
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def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,
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ProcM3,
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FeaturePreferBranchAlign32,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
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ProcM3,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
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FeatureVFP4_D16_SP,
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FeaturePreferBranchAlign32,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em,
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ProcM7,
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FeatureFPARMv8_D16,
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FeaturePreferBranchAlign64,
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FeatureUseMIPipeliner,
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FeatureUseMISched]>;
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def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
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FeatureNoMovt,
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FeatureHasNoBranchPredictor]>;
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def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
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FeatureDSP,
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FeatureFPARMv8_D16_SP,
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FeaturePreferBranchAlign32,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor,
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FeatureAvoidMULS,
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FeatureFixCMSE_CVE_2021_35465]>;
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def : ProcessorModel<"star-mc1", CortexM4Model, [ARMv8mMainline,
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FeatureDSP,
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FeatureFPARMv8_D16_SP,
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FeaturePreferBranchAlign32,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor,
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FeatureAvoidMULS,
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FeatureFixCMSE_CVE_2021_35465]>;
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def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
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FeatureDSP,
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FeatureFPARMv8_D16_SP,
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FeaturePreferBranchAlign32,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVFMx,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor,
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FeatureFixCMSE_CVE_2021_35465]>;
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def : ProcessorModel<"cortex-m55", CortexM55Model, [ARMv81mMainline,
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ProcM55,
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FeatureDSP,
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FeatureFPARMv8_D16,
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FeatureUseMISched,
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FeatureHasNoBranchPredictor,
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FeaturePreferBranchAlign32,
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FeatureHasSlowFPVMLx,
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HasMVEFloatOps,
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FeatureFixCMSE_CVE_2021_35465]>;
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def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline,
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ProcM85,
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FeatureDSP,
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FeatureFPARMv8_D16,
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FeaturePACBTI,
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FeaturePreferBranchAlign64,
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FeatureUseMISched,
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HasMVEFloatOps]>;
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def : ProcessorModel<"cortex-m52", CortexM55Model, [ARMv81mMainline,
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FeatureDSP,
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FeatureFPARMv8_D16,
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FeatureHasNoBranchPredictor,
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FeaturePACBTI,
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FeatureUseMISched,
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FeaturePreferBranchAlign32,
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FeatureHasSlowFPVMLx,
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FeatureMVEVectorCostFactor1,
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HasMVEFloatOps]>;
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def : ProcNoItin<"cortex-a32", [ARMv8a,
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FeatureHWDivThumb,
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FeatureHWDivARM,
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FeatureCrypto,
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
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FeatureHWDivThumb,
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FeatureHWDivARM,
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FeatureCrypto,
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
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FeatureHWDivThumb,
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FeatureHWDivARM,
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FeatureCrypto,
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FeatureCRC,
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FeatureFPAO]>;
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def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57,
|
|
FeatureHWDivThumb,
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|
FeatureHWDivARM,
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|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFPAO,
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|
FeatureAvoidPartialCPSR,
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|
FeatureCheapPredicableCPSR,
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|
FeatureFixCortexA57AES1742098]>;
|
|
|
|
def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFixCortexA57AES1742098]>;
|
|
|
|
def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-a77", [ARMv82a, ProcA77,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-a78ae", [ARMv82a, ProcA78AE,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureDotProd,
|
|
FeatureFullFP16]>;
|
|
|
|
def : ProcNoItin<"cortex-a510", [ARMv9a, ProcA710,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureFP16FML,
|
|
FeatureBF16,
|
|
FeatureMatMulInt8,
|
|
FeatureSB]>;
|
|
|
|
def : ProcNoItin<"cortex-a710", [ARMv9a, ProcA710,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureFP16FML,
|
|
FeatureBF16,
|
|
FeatureMatMulInt8,
|
|
FeatureSB]>;
|
|
|
|
def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"cortex-x1c", [ARMv82a, ProcX1C,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"neoverse-v1", [ARMv84a,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureFullFP16,
|
|
FeatureBF16,
|
|
FeatureMatMulInt8]>;
|
|
|
|
def : ProcNoItin<"neoverse-n1", [ARMv82a,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"neoverse-n2", [ARMv9a,
|
|
FeatureBF16,
|
|
FeatureFP16FML,
|
|
FeatureMatMulInt8]>;
|
|
|
|
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
|
|
FeatureHasRetAddrStack,
|
|
FeatureNEONForFP,
|
|
FeatureVFP4,
|
|
FeatureMP,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureAvoidPartialCPSR,
|
|
FeatureAvoidMOVsShOp,
|
|
FeatureHasSlowFPVMLx,
|
|
FeatureHasSlowFPVFMx,
|
|
FeatureCrypto,
|
|
FeatureUseMISched,
|
|
FeatureZCZeroing,
|
|
FeatureNoPostRASched]>;
|
|
|
|
def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>;
|
|
def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos,
|
|
FeatureFullFP16,
|
|
FeatureDotProd]>;
|
|
|
|
def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
|
|
FeatureHWDivThumb,
|
|
FeatureHWDivARM,
|
|
FeatureCrypto,
|
|
FeatureCRC]>;
|
|
|
|
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
|
|
FeatureFPARMv8,
|
|
FeatureNEON,
|
|
FeatureUseMISched,
|
|
FeatureFPAO]>;
|
|
|
|
def : ProcessorModel<"cortex-r52plus", CortexR52Model, [ARMv8r, ProcR52plus,
|
|
FeatureFPARMv8,
|
|
FeatureNEON,
|
|
FeatureUseMISched,
|
|
FeatureFPAO]>;
|