shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
llvm-project/llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll
Alexander Richardson 3a4b351ba1
[IR] Introduce the ptrtoaddr instruction 
This introduces a new `ptrtoaddr` instruction which is similar to
`ptrtoint` but has two differences:

1) Unlike `ptrtoint`, `ptrtoaddr` does not capture provenance
2) `ptrtoaddr` only extracts (and then extends/truncates) the low
   index-width bits of the pointer

For most architectures, difference 2) does not matter since index (address)
width and pointer representation width are the same, but this does make a
difference for architectures that have pointers that aren't just plain
integer addresses such as AMDGPU fat pointers or CHERI capabilities.

This commit introduces textual and bitcode IR support as well as basic code
generation, but optimization passes do not handle the new instruction yet
so it may result in worse code than using ptrtoint. Follow-up changes will
update capture tracking, etc. for the new instruction.

RFC: https://discourse.llvm.org/t/clarifiying-the-semantics-of-ptrtoint/83987/54

Reviewed By: nikic

Pull Request: https://github.com/llvm/llvm-project/pull/139357
2025-08-08 10:12:39 -07:00

196 lines
12 KiB
LLVM
Raw Permalink Blame History

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=normalize < %s | FileCheck %s
define void @test(ptr, i32) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[A0:%.*]], i32 [[A1:%.*]]) {
; CHECK-NEXT: [[BB76951:.*]]:
; CHECK-NEXT: %"vl72693([[A1]], 1)" = add i32 [[A1]], 1
; CHECK-NEXT: br label %[[BB16110:.*]]
; CHECK: [[BB16110]]:
; CHECK-NEXT: %"op81283(op18080, vl72693)" = phi i32 [ %"op18080(op10412, op18131)", %[[BB16110]] ], [ %"vl72693([[A1]], 1)", %[[BB76951]] ]
; CHECK-NEXT: %"op81283(op18131, vl72693)" = phi i32 [ %"op18131(op81283)70", %[[BB16110]] ], [ %"vl72693([[A1]], 1)", %[[BB76951]] ]
; CHECK-NEXT: %"op13219(op81283)" = mul i32 %"op81283(op18080, vl72693)", undef
; CHECK-NEXT: %"op16562(op13219)" = xor i32 -1, %"op13219(op81283)"
; CHECK-NEXT: %"op12556(op16562, op81283)" = add i32 %"op16562(op13219)", %"op81283(op18080, vl72693)"
; CHECK-NEXT: %"op18131(op81283)" = add i32 -1, %"op81283(op18131, vl72693)"
; CHECK-NEXT: %"op18080(op12556, op18131)" = add i32 %"op12556(op16562, op81283)", %"op18131(op81283)"
; CHECK-NEXT: %"op17720(op13219, op18080)" = mul i32 %"op13219(op81283)", %"op18080(op12556, op18131)"
; CHECK-NEXT: %"op16562(op17720)" = xor i32 -1, %"op17720(op13219, op18080)"
; CHECK-NEXT: %"op17430(op16562, op18080)" = add i32 %"op16562(op17720)", %"op18080(op12556, op18131)"
; CHECK-NEXT: %"op10412(op17430)" = add i32 %"op17430(op16562, op18080)", undef
; CHECK-NEXT: %"op17720(op10412, op17720)" = mul i32 %"op10412(op17430)", %"op17720(op13219, op18080)"
; CHECK-NEXT: %"op16562(op17720)1" = xor i32 -1, %"op17720(op10412, op17720)"
; CHECK-NEXT: %"op17430(op10412, op16562)" = add i32 %"op10412(op17430)", %"op16562(op17720)1"
; CHECK-NEXT: %"op10412(op17430)2" = add i32 %"op17430(op10412, op16562)", undef
; CHECK-NEXT: %"op10412(op10412)" = add i32 %"op10412(op17430)2", undef
; CHECK-NEXT: %"op10412(op10412)3" = add i32 %"op10412(op10412)", undef
; CHECK-NEXT: %"op17720(op10412, op17720)4" = mul i32 %"op10412(op17430)2", %"op17720(op10412, op17720)"
; CHECK-NEXT: %"op17720(op10412, op17720)5" = mul i32 %"op10412(op10412)3", %"op17720(op10412, op17720)4"
; CHECK-NEXT: %"op16562(op17720)6" = xor i32 -1, %"op17720(op10412, op17720)5"
; CHECK-NEXT: %"op17430(op10412, op16562)7" = add i32 %"op10412(op10412)3", %"op16562(op17720)6"
; CHECK-NEXT: %"op10412(op17430)8" = add i32 %"op17430(op10412, op16562)7", undef
; CHECK-NEXT: %"op17720(op10412, op17720)9" = mul i32 %"op10412(op17430)8", %"op17720(op10412, op17720)5"
; CHECK-NEXT: %"op16562(op17720)10" = xor i32 -1, %"op17720(op10412, op17720)9"
; CHECK-NEXT: %"op17430(op10412, op16562)11" = add i32 %"op10412(op17430)8", %"op16562(op17720)10"
; CHECK-NEXT: %"op10412(op17430)12" = add i32 %"op17430(op10412, op16562)11", undef
; CHECK-NEXT: %"op17720(op10412, op17720)13" = mul i32 %"op10412(op17430)12", %"op17720(op10412, op17720)9"
; CHECK-NEXT: %"op16562(op17720)14" = xor i32 -1, %"op17720(op10412, op17720)13"
; CHECK-NEXT: %"op17430(op10412, op16562)15" = add i32 %"op10412(op17430)12", %"op16562(op17720)14"
; CHECK-NEXT: %"op10412(op17430)16" = add i32 %"op17430(op10412, op16562)15", undef
; CHECK-NEXT: %"op17720(op10412, op17720)17" = mul i32 %"op10412(op17430)16", %"op17720(op10412, op17720)13"
; CHECK-NEXT: %"op16562(op17720)18" = xor i32 -1, %"op17720(op10412, op17720)17"
; CHECK-NEXT: %"op17430(op10412, op16562)19" = add i32 %"op10412(op17430)16", %"op16562(op17720)18"
; CHECK-NEXT: %"op10412(op17430)20" = add i32 %"op17430(op10412, op16562)19", undef
; CHECK-NEXT: %"op17720(op10412, op17720)21" = mul i32 %"op10412(op17430)20", %"op17720(op10412, op17720)17"
; CHECK-NEXT: %"op16562(op17720)22" = xor i32 -1, %"op17720(op10412, op17720)21"
; CHECK-NEXT: %"op17430(op10412, op16562)23" = add i32 %"op10412(op17430)20", %"op16562(op17720)22"
; CHECK-NEXT: %"op18131(op81283)24" = add i32 -9, %"op81283(op18131, vl72693)"
; CHECK-NEXT: %"op18080(op17430, op18131)" = add i32 %"op17430(op10412, op16562)23", %"op18131(op81283)24"
; CHECK-NEXT: %"op17720(op17720, op18080)" = mul i32 %"op17720(op10412, op17720)21", %"op18080(op17430, op18131)"
; CHECK-NEXT: %"op16562(op17720)25" = xor i32 -1, %"op17720(op17720, op18080)"
; CHECK-NEXT: %"op17430(op16562, op18080)26" = add i32 %"op16562(op17720)25", %"op18080(op17430, op18131)"
; CHECK-NEXT: %"op10412(op17430)27" = add i32 %"op17430(op16562, op18080)26", undef
; CHECK-NEXT: %"op17720(op10412, op17720)28" = mul i32 %"op10412(op17430)27", %"op17720(op17720, op18080)"
; CHECK-NEXT: %"op16562(op17720)29" = xor i32 -1, %"op17720(op10412, op17720)28"
; CHECK-NEXT: %"op17430(op10412, op16562)30" = add i32 %"op10412(op17430)27", %"op16562(op17720)29"
; CHECK-NEXT: %"op10412(op17430)31" = add i32 %"op17430(op10412, op16562)30", undef
; CHECK-NEXT: %"op17720(op10412, op17720)32" = mul i32 %"op10412(op17430)31", %"op17720(op10412, op17720)28"
; CHECK-NEXT: %"op16562(op17720)33" = xor i32 -1, %"op17720(op10412, op17720)32"
; CHECK-NEXT: %"op17430(op10412, op16562)34" = add i32 %"op10412(op17430)31", %"op16562(op17720)33"
; CHECK-NEXT: %"op10412(op17430)35" = add i32 %"op17430(op10412, op16562)34", undef
; CHECK-NEXT: %"op17720(op10412, op17720)36" = mul i32 %"op10412(op17430)35", %"op17720(op10412, op17720)32"
; CHECK-NEXT: %"op16562(op17720)37" = xor i32 -1, %"op17720(op10412, op17720)36"
; CHECK-NEXT: %"op17430(op10412, op16562)38" = add i32 %"op10412(op17430)35", %"op16562(op17720)37"
; CHECK-NEXT: %"op10412(op17430)39" = add i32 %"op17430(op10412, op16562)38", undef
; CHECK-NEXT: %"op17720(op10412, op17720)40" = mul i32 %"op10412(op17430)39", %"op17720(op10412, op17720)36"
; CHECK-NEXT: %"op16562(op17720)41" = xor i32 -1, %"op17720(op10412, op17720)40"
; CHECK-NEXT: %"op17430(op10412, op16562)42" = add i32 %"op10412(op17430)39", %"op16562(op17720)41"
; CHECK-NEXT: %"op18131(op81283)43" = add i32 -14, %"op81283(op18131, vl72693)"
; CHECK-NEXT: %"op18080(op17430, op18131)44" = add i32 %"op17430(op10412, op16562)42", %"op18131(op81283)43"
; CHECK-NEXT: %"op17720(op17720, op18080)45" = mul i32 %"op17720(op10412, op17720)40", %"op18080(op17430, op18131)44"
; CHECK-NEXT: %"op16562(op17720)46" = xor i32 -1, %"op17720(op17720, op18080)45"
; CHECK-NEXT: %"op17430(op16562, op18080)47" = add i32 %"op16562(op17720)46", %"op18080(op17430, op18131)44"
; CHECK-NEXT: %"op10412(op17430)48" = add i32 %"op17430(op16562, op18080)47", undef
; CHECK-NEXT: %"op17720(op10412, op17720)49" = mul i32 %"op10412(op17430)48", %"op17720(op17720, op18080)45"
; CHECK-NEXT: %"op16562(op17720)50" = xor i32 -1, %"op17720(op10412, op17720)49"
; CHECK-NEXT: %"op17430(op10412, op16562)51" = add i32 %"op10412(op17430)48", %"op16562(op17720)50"
; CHECK-NEXT: %"op10412(op17430)52" = add i32 %"op17430(op10412, op16562)51", undef
; CHECK-NEXT: %"op17720(op10412, op17720)53" = mul i32 %"op10412(op17430)52", %"op17720(op10412, op17720)49"
; CHECK-NEXT: %"op16562(op17720)54" = xor i32 -1, %"op17720(op10412, op17720)53"
; CHECK-NEXT: %"op17430(op10412, op16562)55" = add i32 %"op10412(op17430)52", %"op16562(op17720)54"
; CHECK-NEXT: %"op10412(op17430)56" = add i32 %"op17430(op10412, op16562)55", undef
; CHECK-NEXT: %"op17720(op10412, op17720)57" = mul i32 %"op10412(op17430)56", %"op17720(op10412, op17720)53"
; CHECK-NEXT: %"op16562(op17720)58" = xor i32 -1, %"op17720(op10412, op17720)57"
; CHECK-NEXT: %"op17430(op10412, op16562)59" = add i32 %"op10412(op17430)56", %"op16562(op17720)58"
; CHECK-NEXT: %"op10412(op17430)60" = add i32 %"op17430(op10412, op16562)59", undef
; CHECK-NEXT: %"op17720(op10412, op17720)61" = mul i32 %"op10412(op17430)60", %"op17720(op10412, op17720)57"
; CHECK-NEXT: %"op16562(op17720)62" = xor i32 -1, %"op17720(op10412, op17720)61"
; CHECK-NEXT: %"op17430(op10412, op16562)63" = add i32 %"op10412(op17430)60", %"op16562(op17720)62"
; CHECK-NEXT: %"op10412(op17430)64" = add i32 %"op17430(op10412, op16562)63", undef
; CHECK-NEXT: %"op17720(op10412, op17720)65" = mul i32 %"op10412(op17430)64", %"op17720(op10412, op17720)61"
; CHECK-NEXT: %"op16562(op17720)66" = xor i32 -1, %"op17720(op10412, op17720)65"
; CHECK-NEXT: %"op17430(op10412, op16562)67" = add i32 %"op10412(op17430)64", %"op16562(op17720)66"
; CHECK-NEXT: %"op10412(op17430)68" = add i32 %"op17430(op10412, op16562)67", undef
; CHECK-NEXT: %"op10412(op10412)69" = add i32 %"op10412(op17430)68", undef
; CHECK-NEXT: %"op18131(op81283)70" = add i32 -21, %"op81283(op18131, vl72693)"
; CHECK-NEXT: %"op18080(op10412, op18131)" = add i32 %"op10412(op10412)69", %"op18131(op81283)70"
; CHECK-NEXT: store i32 %"op18080(op10412, op18131)", ptr [[A0]], align 4
; CHECK-NEXT: br label %[[BB16110]]
;
bb:
%a = add i32 %1, 1
br label %bb1
bb1: ; preds = %bb1, %bb
%tmp = phi i32 [ %a, %bb ], [ %tmp87, %bb1 ]
%tmp2 = phi i32 [ %a, %bb ], [ %tmp86, %bb1 ]
%tmp3 = mul i32 %tmp, undef
%tmp4 = xor i32 %tmp3, -1
%tmp5 = add i32 %tmp, %tmp4
%tmp6 = add i32 %tmp2, -1
%tmp7 = add i32 %tmp5, %tmp6
%tmp8 = mul i32 %tmp7, %tmp3
%tmp9 = xor i32 %tmp8, -1
%tmp10 = add i32 %tmp7, %tmp9
%tmp11 = add i32 %tmp10, undef
%tmp12 = mul i32 %tmp11, %tmp8
%tmp13 = xor i32 %tmp12, -1
%tmp14 = add i32 %tmp11, %tmp13
%tmp15 = add i32 %tmp14, undef
%tmp16 = mul i32 %tmp15, %tmp12
%tmp17 = add i32 %tmp15, undef
%tmp18 = add i32 %tmp17, undef
%tmp19 = mul i32 %tmp18, %tmp16
%tmp20 = xor i32 %tmp19, -1
%tmp21 = add i32 %tmp18, %tmp20
%tmp22 = add i32 %tmp21, undef
%tmp23 = mul i32 %tmp22, %tmp19
%tmp24 = xor i32 %tmp23, -1
%tmp25 = add i32 %tmp22, %tmp24
%tmp26 = add i32 %tmp25, undef
%tmp27 = mul i32 %tmp26, %tmp23
%tmp28 = xor i32 %tmp27, -1
%tmp29 = add i32 %tmp26, %tmp28
%tmp30 = add i32 %tmp29, undef
%tmp31 = mul i32 %tmp30, %tmp27
%tmp32 = xor i32 %tmp31, -1
%tmp33 = add i32 %tmp30, %tmp32
%tmp34 = add i32 %tmp33, undef
%tmp35 = mul i32 %tmp34, %tmp31
%tmp36 = xor i32 %tmp35, -1
%tmp37 = add i32 %tmp34, %tmp36
%tmp38 = add i32 %tmp2, -9
%tmp39 = add i32 %tmp37, %tmp38
%tmp40 = mul i32 %tmp39, %tmp35
%tmp41 = xor i32 %tmp40, -1
%tmp42 = add i32 %tmp39, %tmp41
%tmp43 = add i32 %tmp42, undef
%tmp44 = mul i32 %tmp43, %tmp40
%tmp45 = xor i32 %tmp44, -1
%tmp46 = add i32 %tmp43, %tmp45
%tmp47 = add i32 %tmp46, undef
%tmp48 = mul i32 %tmp47, %tmp44
%tmp49 = xor i32 %tmp48, -1
%tmp50 = add i32 %tmp47, %tmp49
%tmp51 = add i32 %tmp50, undef
%tmp52 = mul i32 %tmp51, %tmp48
%tmp53 = xor i32 %tmp52, -1
%tmp54 = add i32 %tmp51, %tmp53
%tmp55 = add i32 %tmp54, undef
%tmp56 = mul i32 %tmp55, %tmp52
%tmp57 = xor i32 %tmp56, -1
%tmp58 = add i32 %tmp55, %tmp57
%tmp59 = add i32 %tmp2, -14
%tmp60 = add i32 %tmp58, %tmp59
%tmp61 = mul i32 %tmp60, %tmp56
%tmp62 = xor i32 %tmp61, -1
%tmp63 = add i32 %tmp60, %tmp62
%tmp64 = add i32 %tmp63, undef
%tmp65 = mul i32 %tmp64, %tmp61
%tmp66 = xor i32 %tmp65, -1
%tmp67 = add i32 %tmp64, %tmp66
%tmp68 = add i32 %tmp67, undef
%tmp69 = mul i32 %tmp68, %tmp65
%tmp70 = xor i32 %tmp69, -1
%tmp71 = add i32 %tmp68, %tmp70
%tmp72 = add i32 %tmp71, undef
%tmp73 = mul i32 %tmp72, %tmp69
%tmp74 = xor i32 %tmp73, -1
%tmp75 = add i32 %tmp72, %tmp74
%tmp76 = add i32 %tmp75, undef
%tmp77 = mul i32 %tmp76, %tmp73
%tmp78 = xor i32 %tmp77, -1
%tmp79 = add i32 %tmp76, %tmp78
%tmp80 = add i32 %tmp79, undef
%tmp81 = mul i32 %tmp80, %tmp77
%tmp82 = xor i32 %tmp81, -1
%tmp83 = add i32 %tmp80, %tmp82
%tmp84 = add i32 %tmp83, undef
%tmp85 = add i32 %tmp84, undef
%tmp86 = add i32 %tmp2, -21
%tmp87 = add i32 %tmp85, %tmp86
store i32 %tmp87, ptr %0
br label %bb1
}
Reference in New Issue View Git Blame Copy Permalink