fa3ec0c17c
Materialize constant vector trip counts before ::execute, if the trip count can be computed as Original (TC / (VF * UF)) * (VF * UF). For now this excludes when the tail is folded or scalar epilogues are required. This enables removing a number of redundant branches from the middle block. For now this is also only done when not vectorizing the epilogue, as the simplification complicates stitching the 2 plans together. PR: https://github.com/llvm/llvm-project/pull/142309
216 lines
10 KiB
LLVM
216 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; REQUIRES: asserts
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; RUN: opt < %s -passes='function(loop-vectorize,instcombine)' -force-vector-width=2 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: phi_two_incoming_values
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; CHECK: LV: Found an estimated cost of 1 for VF 2 For instruction: %i = phi i64 [ %i.next, %if.end ], [ 0, %entry ]
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; CHECK: LV: Found an estimated cost of 1 for VF 2 For instruction: %tmp5 = phi i32 [ %tmp1, %for.body ], [ %tmp4, %if.then ]
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;
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define void @phi_two_incoming_values(ptr noalias %a, ptr noalias %b, i64 %n) {
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; CHECK-LABEL: define void @phi_two_incoming_values(
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; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], -2
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
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; CHECK-NEXT: [[PREDPHI:%.*]] = add <2 x i32> [[WIDE_LOAD]], [[TMP5]]
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; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP3]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[FOR_BODY:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[IF_END:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[I]]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP2]], 0
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; CHECK-NEXT: br i1 [[TMP4]], label %[[IF_THEN:.*]], label %[[IF_END]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw i32 [[TMP2]], 1
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; CHECK-NEXT: br label %[[IF_END]]
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[TMP6:%.*]] = phi i32 [ [[TMP2]], %[[FOR_BODY]] ], [ [[TMP5]], %[[IF_THEN]] ]
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; CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP3]], align 4
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; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[I]], [[N]]
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; CHECK-NEXT: br i1 [[COND]], label %[[FOR_END]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %if.end ], [ 0, %entry ]
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%tmp0 = getelementptr inbounds i32, ptr %a, i64 %i
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%tmp1 = load i32, ptr %tmp0, align 4
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%tmp2 = getelementptr inbounds i32, ptr %b, i64 %i
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%tmp3 = icmp sgt i32 %tmp1, 0
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br i1 %tmp3, label %if.then, label %if.end
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if.then:
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%tmp4 = add i32 %tmp1, 1
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br label %if.end
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if.end:
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%tmp5 = phi i32 [ %tmp1, %for.body ], [ %tmp4, %if.then ]
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store i32 %tmp5, ptr %tmp2, align 4
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%i.next = add i64 %i, 1
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%cond = icmp eq i64 %i, %n
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br i1 %cond, label %for.end, label %for.body
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for.end:
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ret void
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}
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; CHECK-LABEL: phi_three_incoming_values
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; CHECK: LV: Found an estimated cost of 1 for VF 2 For instruction: %i = phi i64 [ %i.next, %if.end ], [ 0, %entry ]
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; CHECK: LV: Found an estimated cost of 2 for VF 2 For instruction: %tmp8 = phi i32 [ 9, %for.body ], [ 3, %if.then ], [ %tmp7, %if.else ]
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;
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define void @phi_three_incoming_values(ptr noalias %a, ptr noalias %b, i64 %n) {
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; CHECK-LABEL: define void @phi_three_incoming_values(
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; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], -2
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD]], [[WIDE_LOAD2]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD]], splat (i32 19)
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; CHECK-NEXT: [[TMP7:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD2]], splat (i32 4)
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; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP7]], <2 x i32> splat (i32 4), <2 x i32> splat (i32 5)
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; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> splat (i32 3), <2 x i32> [[TMP8]]
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; CHECK-NEXT: [[PREDPHI3:%.*]] = select <2 x i1> [[TMP5]], <2 x i32> [[PREDPHI]], <2 x i32> splat (i32 9)
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; CHECK-NEXT: store <2 x i32> [[PREDPHI3]], ptr [[TMP3]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[FOR_BODY:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], %[[IF_END:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[I]]
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[I]]
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; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
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; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt i32 [[TMP3]], [[TMP5]]
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; CHECK-NEXT: br i1 [[TMP6]], label %[[IF_THEN:.*]], label %[[IF_END]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP3]], 19
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; CHECK-NEXT: br i1 [[TMP7]], label %[[IF_END]], label %[[IF_ELSE:.*]]
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; CHECK: [[IF_ELSE]]:
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; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP5]], 4
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; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 4, i32 5
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; CHECK-NEXT: br label %[[IF_END]]
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[TMP10:%.*]] = phi i32 [ 9, %[[FOR_BODY]] ], [ 3, %[[IF_THEN]] ], [ [[TMP9]], %[[IF_ELSE]] ]
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; CHECK-NEXT: store i32 [[TMP10]], ptr [[TMP0]], align 4
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; CHECK-NEXT: [[I_NEXT]] = add i64 [[I]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[I]], [[N]]
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; CHECK-NEXT: br i1 [[COND]], label %[[FOR_END]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %if.end ], [ 0, %entry ]
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%tmp0 = getelementptr inbounds i32, ptr %a, i64 %i
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%tmp1 = load i32, ptr %tmp0, align 4
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%tmp2 = getelementptr inbounds i32, ptr %b, i64 %i
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%tmp3 = load i32, ptr %tmp2, align 4
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%tmp4 = icmp sgt i32 %tmp1, %tmp3
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br i1 %tmp4, label %if.then, label %if.end
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if.then:
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%tmp5 = icmp sgt i32 %tmp1, 19
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br i1 %tmp5, label %if.end, label %if.else
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if.else:
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%tmp6 = icmp slt i32 %tmp3, 4
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%tmp7 = select i1 %tmp6, i32 4, i32 5
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br label %if.end
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if.end:
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%tmp8 = phi i32 [ 9, %for.body ], [ 3, %if.then ], [ %tmp7, %if.else ]
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store i32 %tmp8, ptr %tmp0, align 4
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%i.next = add i64 %i, 1
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%cond = icmp eq i64 %i, %n
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br i1 %cond, label %for.end, label %for.body
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for.end:
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ret void
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}
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; Test case for https://github.com/llvm/llvm-project/issues/113794.
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define i32 @red_phi_0(i32 %start, ptr %src) {
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; CHECK-LABEL: define i32 @red_phi_0(
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; CHECK-SAME: i32 [[START:%.*]], ptr [[SRC:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[START]], i64 0
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP0]])
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: br i1 poison, label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i32 [ poison, %[[LOOP]] ], [ [[TMP2]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%red = phi i32 [ %start, %entry ], [ %red.next, %loop ]
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%red.next = add i32 0, %red
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%iv.next = add i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, 100
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br i1 %exitcond.not, label %exit, label %loop
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exit:
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%res = phi i32 [ %red.next, %loop ]
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ret i32 %res
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}
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