Diana Picus 0091cc3528 [ARM] GlobalISel: Constrain callee register on indirect calls ...

When lowering calls, we generate instructions with machine opcodes
rather than generic ones. Therefore, we need to constrain the register
classes of the operands.

Also enable the machine verifier on the arm-irtranslator.ll test, since
that would've caught this issue.

Fixes (part of) PR32146.

llvm-svn: 304712

2017-06-05 12:54:53 +00:00

..

AArch64

Fix addcarry-crash.ll

2017-06-01 14:24:31 +00:00

AMDGPU

[AMDGPU] Fix SIFoldOperands crash with clamp

2017-06-05 01:03:04 +00:00

ARM

[ARM] GlobalISel: Constrain callee register on indirect calls

2017-06-05 12:54:53 +00:00

AVR

[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi

2017-05-31 06:27:46 +00:00

BPF

[bpf] fix a bug which causes incorrect big endian reloc fixup

2017-05-05 18:05:00 +00:00

Generic

[LegacyPassManager] Remove TargetMachine constructors

2017-05-18 17:21:13 +00:00

Hexagon

[Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist

2017-06-02 14:07:06 +00:00

Inputs

…

Lanai

CodeGen: Rename DEBUG_TYPE to match passnames

2017-05-25 21:26:32 +00:00

Mips

[mips][microMIPS] Extending size reduction pass with LBU16, LHU16, SB16 and SH16

2017-06-02 14:14:21 +00:00

MIR

[RABasic] Properly initialize the pass

2017-06-02 22:46:26 +00:00

MSP430

[MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex.

2017-05-24 15:08:30 +00:00

Nios2

[Nios2] Target registration

2017-05-29 09:48:30 +00:00

NVPTX

Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."

2017-05-18 18:50:05 +00:00

PowerPC

RegisterScavenging: Add ScavengerTest pass

2017-06-02 23:01:42 +00:00

SPARC

Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."

2017-05-18 18:50:05 +00:00

SystemZ

[SystemZ] Simplify test case. NFC

2017-06-02 23:40:58 +00:00

Thumb

Move machine-cse-physreg.mir to test/CodeGen/Thumb

2017-05-24 17:20:47 +00:00

Thumb2

MIR: remove explicit "noVRegs" property.

2017-05-30 21:28:57 +00:00

WebAssembly

[wasm] Fix test after r304117.

2017-05-29 16:32:52 +00:00

WinEH

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X86

[X86][SSE] Change BUILD_VECTOR interleaving ordering to improve coalescing/combine opportunities

2017-06-04 20:12:04 +00:00

XCore

AsmPrinter: mark the beginning and the end of a function in verbose mode

2017-05-23 21:22:16 +00:00