33fd4a18e7
Get rid of all fixmes and base heuristic on `num-clustered-dwords`. The main intuition behind this is as follows. The existing heuristic roughly summarizes as below: * Assume, all the mem ops instructions participating in the clustering process, loads/stores same num bytes * If num bytes loaded by each mem op is 4 bytes, then cluster at max 5 mem ops, that is at max 20 bytes * If num bytes loaded by each mem op is 8 bytes, then cluster at max 3 mem ops, that is at max 24 bytes * If num bytes loaded by each mem op is 16 bytes, then cluster at max 2 mem ops, that is at max 32 bytes So, we need to make sure that the new heuristic do not completey deviate away from the above one, and it properly handles both the sub-word loads and the wide loads. Reviewed By: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D84354
59 lines
2.8 KiB
LLVM
59 lines
2.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-TFILD %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -combiner-tokenfactor-inline-limit=7 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN-TFIL7 %s
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; GCN-LABEL: {{^}}token_factor_inline_limit_test:
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; GCN-TFILD: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
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; GCN-TFILD: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
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; GCN-TFILD: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
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; GCN-TFILD: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
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; GCN-TFILD: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
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; GCN-TFILD: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
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; GCN-TFILD: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
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; GCN-TFILD: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
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; GCN-TFILD: buffer_store_dword [[REG8]], {{.*$}}
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; GCN-TFILD: buffer_store_dword [[REG9]], {{.*}} offset:4
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; GCN-TFILD: buffer_store_dword [[REG10]], {{.*}} offset:8
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; GCN-TFILD: buffer_store_dword [[REG11]], {{.*}} offset:12
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; GCN-TFILD: buffer_store_dword [[REG12]], {{.*}} offset:16
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; GCN-TFILD: buffer_store_dword [[REG13]], {{.*}} offset:20
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; GCN-TFILD: buffer_store_dword [[REG14]], {{.*}} offset:24
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; GCN-TFILD: buffer_store_dword [[REG15]], {{.*}} offset:28
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; GCN-TFIL7: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
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; GCN-TFIL7: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
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; GCN-TFIL7: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
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; GCN-TFIL7: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
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; GCN-TFIL7: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
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; GCN-TFIL7: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
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; GCN-TFIL7: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
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; GCN-TFIL7: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
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; GCN-TFIL7: buffer_store_dword [[REG15]], {{.*}} offset:28
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; GCN-TFIL7: buffer_store_dword [[REG14]], {{.*}} offset:24
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; GCN-TFIL7: buffer_store_dword [[REG13]], {{.*}} offset:20
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; GCN-TFIL7: buffer_store_dword [[REG12]], {{.*}} offset:16
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; GCN-TFIL7: buffer_store_dword [[REG11]], {{.*}} offset:12
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; GCN-TFIL7: buffer_store_dword [[REG10]], {{.*}} offset:8
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; GCN-TFIL7: buffer_store_dword [[REG9]], {{.*}} offset:4
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; GCN-TFIL7: buffer_store_dword [[REG8]], {{.*$}}
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; GCN: v_mov_b32_e32 v31, 7
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; GCN: s_getpc
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define void @token_factor_inline_limit_test() {
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entry:
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call void @external_void_func_8xv5i32(
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<5 x i32><i32 0, i32 0, i32 0, i32 0, i32 0>,
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<5 x i32><i32 1, i32 1, i32 1, i32 1, i32 1>,
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<5 x i32><i32 2, i32 2, i32 2, i32 2, i32 2>,
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<5 x i32><i32 3, i32 3, i32 3, i32 3, i32 3>,
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<5 x i32><i32 4, i32 4, i32 4, i32 4, i32 4>,
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<5 x i32><i32 5, i32 5, i32 5, i32 5, i32 5>,
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<5 x i32><i32 6, i32 7, i32 8, i32 9, i32 10>,
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<5 x i32><i32 11, i32 12, i32 13, i32 14, i32 15>)
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ret void
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}
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declare hidden void @external_void_func_8xv5i32(<5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>,
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<5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>)
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