9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}load_i8_sext_private:
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; SI: buffer_load_sbyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i8_sext_private(ptr addrspace(1) %out) {
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entry:
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%tmp0 = alloca i8, addrspace(5)
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%tmp1 = load i8, ptr addrspace(5) %tmp0
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%tmp2 = sext i8 %tmp1 to i32
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i8_zext_private:
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; SI: buffer_load_ubyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i8_zext_private(ptr addrspace(1) %out) {
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entry:
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%tmp0 = alloca i8, addrspace(5)
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%tmp1 = load i8, ptr addrspace(5) %tmp0
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%tmp2 = zext i8 %tmp1 to i32
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i16_sext_private:
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; SI: buffer_load_sshort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}}
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define amdgpu_kernel void @load_i16_sext_private(ptr addrspace(1) %out) {
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entry:
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%tmp0 = alloca i16, addrspace(5)
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%tmp1 = load i16, ptr addrspace(5) %tmp0
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%tmp2 = sext i16 %tmp1 to i32
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}load_i16_zext_private:
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; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 glc{{$}}
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define amdgpu_kernel void @load_i16_zext_private(ptr addrspace(1) %out) {
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entry:
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%tmp0 = alloca i16, addrspace(5)
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%tmp1 = load volatile i16, ptr addrspace(5) %tmp0
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%tmp2 = zext i16 %tmp1 to i32
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store i32 %tmp2, ptr addrspace(1) %out
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ret void
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}
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