2c0a67d6d7
Preserving all analyses likely is a wrong assertion since we do not know what other analyses might exist that we've updated. Updated to preserve CFG, LiveIntervalsAnalysis and SlotIndexAnalysis (which is transitively preserved from LiveIntervalsAnalysis)
106 lines
3.1 KiB
C++
106 lines
3.1 KiB
C++
//===- AArch64PostCoalescerPass.cpp - AArch64 Post Coalescer pass ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "AArch64MachineFunctionInfo.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-post-coalescer-pass"
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namespace {
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struct AArch64PostCoalescer : public MachineFunctionPass {
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static char ID;
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AArch64PostCoalescer() : MachineFunctionPass(ID) {}
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LiveIntervals *LIS;
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MachineRegisterInfo *MRI;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "AArch64 Post Coalescer pass";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervalsWrapperPass>();
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AU.addPreserved<LiveIntervalsWrapperPass>();
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AU.addPreserved<SlotIndexesWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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char AArch64PostCoalescer::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(AArch64PostCoalescer, "aarch64-post-coalescer-pass",
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"AArch64 Post Coalescer Pass", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
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INITIALIZE_PASS_END(AArch64PostCoalescer, "aarch64-post-coalescer-pass",
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"AArch64 Post Coalescer Pass", false, false)
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bool AArch64PostCoalescer::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
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if (!FuncInfo->hasStreamingModeChanges())
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return false;
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MRI = &MF.getRegInfo();
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LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : make_early_inc_range(MBB)) {
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switch (MI.getOpcode()) {
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default:
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break;
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case AArch64::COALESCER_BARRIER_FPR16:
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case AArch64::COALESCER_BARRIER_FPR32:
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case AArch64::COALESCER_BARRIER_FPR64:
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case AArch64::COALESCER_BARRIER_FPR128: {
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Register Src = MI.getOperand(1).getReg();
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Register Dst = MI.getOperand(0).getReg();
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if (Src != Dst)
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MRI->replaceRegWith(Dst, Src);
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if (MI.getOperand(1).isUndef())
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for (MachineOperand &MO : MRI->use_operands(Dst))
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MO.setIsUndef();
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// MI must be erased from the basic block before recalculating the live
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// interval.
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LIS->RemoveMachineInstrFromMaps(MI);
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MI.eraseFromParent();
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LIS->removeInterval(Src);
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LIS->createAndComputeVirtRegInterval(Src);
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Changed = true;
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break;
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}
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}
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}
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}
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return Changed;
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}
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FunctionPass *llvm::createAArch64PostCoalescerPass() {
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return new AArch64PostCoalescer();
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}
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