6e2a720dd1
See: https://github.com/llvm/llvm-project/issues/131779 Extends uniformity analysis to support instructions whose uniformity depends on which specific operands are uniform. Introduces `InstructionUniformity::Custom` and a target hook `TTI::isUniform(I, UniformArgs)` that allows targets to define custom uniformity rules. During propagation, custom candidates are checked via the target hook. If we can prove they are uniform, we skip marking them divergent and let iterative propagation re-evaluate as operands change. Implements AMDGPU's `llvm.amdgcn.wave.shuffle` rules (uniform when either operand is uniform, divergent only when both are divergent) as the motivating example. This inverted-logic approach is critical for correctness: proving uniformity early during propagation would be unsafe, as operands can transition from uniform to divergent during divergence propagation. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
332 lines
13 KiB
C++
332 lines
13 KiB
C++
//===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfoImplBase conforming object specific to the
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/// AMDGPU target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#include "AMDGPU.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Support/AMDGPUAddrSpace.h"
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#include <optional>
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namespace llvm {
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class AMDGPUTargetMachine;
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class GCNSubtarget;
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class InstCombiner;
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class Loop;
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class ScalarEvolution;
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class SITargetLowering;
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class Type;
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class Value;
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class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
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using BaseT = BasicTTIImplBase<AMDGPUTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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Triple TargetTriple;
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const TargetSubtargetInfo *ST;
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const TargetLoweringBase *TLI;
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const TargetSubtargetInfo *getST() const { return ST; }
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const TargetLoweringBase *getTLI() const { return TLI; }
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public:
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explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE) const override;
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP) const override;
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uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
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};
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class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
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using BaseT = BasicTTIImplBase<GCNTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const GCNSubtarget *ST;
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const SITargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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bool IsGraphics;
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bool HasFP32Denormals;
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bool HasFP64FP16Denormals;
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static constexpr bool InlinerVectorBonusPercent = 0;
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static const FeatureBitset InlineFeatureIgnoreList;
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const GCNSubtarget *getST() const { return ST; }
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const SITargetLowering *getTLI() const { return TLI; }
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static inline int getFullRateInstrCost() {
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return TargetTransformInfo::TCC_Basic;
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}
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static inline int getHalfRateInstrCost(TTI::TargetCostKind CostKind) {
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return CostKind == TTI::TCK_CodeSize ? 2
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: 2 * TargetTransformInfo::TCC_Basic;
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}
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// TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
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// should be 2 or 4.
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static inline int getQuarterRateInstrCost(TTI::TargetCostKind CostKind) {
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return CostKind == TTI::TCK_CodeSize ? 2
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: 4 * TargetTransformInfo::TCC_Basic;
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}
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// On some parts, normal fp64 operations are half rate, and others
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// quarter. This also applies to some integer operations.
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int get64BitInstrCost(TTI::TargetCostKind CostKind) const;
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std::pair<InstructionCost, MVT> getTypeLegalizationCost(Type *Ty) const;
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/// \returns true if V might be divergent even when all of its operands
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/// are uniform.
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bool isSourceOfDivergence(const Value *V) const;
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/// Returns true for the target specific set of operations which produce
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/// uniform result even taking non-uniform arguments.
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bool isAlwaysUniform(const Value *V) const;
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public:
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explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
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bool hasBranchDivergence(const Function *F = nullptr) const override;
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE) const override;
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP) const override;
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TTI::PSK_FastHardware;
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}
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unsigned getNumberOfRegisters(unsigned RCID) const override;
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TypeSize
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getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
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unsigned getMinVectorRegisterBitWidth() const override;
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unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override;
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unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const override;
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unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const override;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const override;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const override;
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uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
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Type *getMemcpyLoopLoweringType(
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LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
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unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
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std::optional<uint32_t> AtomicElementSize) const override;
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void getMemcpyLoopResidualLoweringType(
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SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
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unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
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Align SrcAlign, Align DestAlign,
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std::optional<uint32_t> AtomicCpySize) const override;
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unsigned getMaxInterleaveFactor(ElementCount VF) const override;
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bool getTgtMemIntrinsic(IntrinsicInst *Inst,
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MemIntrinsicInfo &Info) const override;
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InstructionCost getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
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TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
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ArrayRef<const Value *> Args = {},
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const Instruction *CxtI = nullptr) const override;
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InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr) const override;
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bool isInlineAsmSourceOfDivergence(const CallInst *CI,
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ArrayRef<unsigned> Indices = {}) const;
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using BaseT::getVectorInstrCost;
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InstructionCost
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getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind,
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unsigned Index, const Value *Op0, const Value *Op1,
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TTI::VectorInstrContext VIC =
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TTI::VectorInstrContext::None) const override;
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bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const;
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bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
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// Address space casts must cast between different address spaces.
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if (FromAS == ToAS)
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return false;
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// Casts between any aliasing address spaces are valid.
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return AMDGPU::addrspacesMayAlias(FromAS, ToAS);
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}
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bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override {
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return AMDGPU::addrspacesMayAlias(AS0, AS1);
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}
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unsigned getFlatAddressSpace() const override {
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// Don't bother running InferAddressSpaces pass on graphics shaders which
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// don't use flat addressing.
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if (IsGraphics)
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return -1;
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return AMDGPUAS::FLAT_ADDRESS;
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}
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bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
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Intrinsic::ID IID) const override;
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bool
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canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override {
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return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS &&
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AS != AMDGPUAS::PRIVATE_ADDRESS;
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}
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Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
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Value *NewV) const override;
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bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0,
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const Value *Op1, InstCombiner &IC) const;
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bool simplifyDemandedLaneMaskArg(InstCombiner &IC, IntrinsicInst &II,
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unsigned LaneAgIdx) const;
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std::optional<Instruction *>
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instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override;
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Value *simplifyAMDGCNLaneIntrinsicDemanded(InstCombiner &IC,
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IntrinsicInst &II,
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const APInt &DemandedElts,
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APInt &UndefElts) const;
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Instruction *hoistLaneIntrinsicThroughOperand(InstCombiner &IC,
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IntrinsicInst &II) const;
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std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
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APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const override;
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InstructionCost getVectorSplitCost() const { return 0; }
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InstructionCost
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getShuffleCost(TTI::ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
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ArrayRef<int> Mask, TTI::TargetCostKind CostKind, int Index,
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VectorType *SubTp, ArrayRef<const Value *> Args = {},
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const Instruction *CxtI = nullptr) const override;
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bool isProfitableToSinkOperands(Instruction *I,
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SmallVectorImpl<Use *> &Ops) const override;
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const override;
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int getInliningLastCallToStaticBonus() const override;
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unsigned getInliningThresholdMultiplier() const override { return 11; }
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unsigned adjustInliningThreshold(const CallBase *CB) const override;
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unsigned getCallerAllocaCost(const CallBase *CB,
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const AllocaInst *AI) const override;
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int getInlinerVectorBonusPercent() const override {
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return InlinerVectorBonusPercent;
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}
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InstructionCost
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getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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std::optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost
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getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind) const override;
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InstructionCost
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getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
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TTI::TargetCostKind CostKind) const override;
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/// Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
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unsigned getCacheLineSize() const override { return 128; }
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/// How much before a load we should place the prefetch instruction.
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/// This is currently measured in number of IR instructions.
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unsigned getPrefetchDistance() const override;
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/// \return if target want to issue a prefetch in address space \p AS.
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bool shouldPrefetchAddressSpace(unsigned AS) const override;
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void collectKernelLaunchBounds(
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const Function &F,
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SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const override;
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enum class KnownIEEEMode { Unknown, On, Off };
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/// Return KnownIEEEMode::On if we know if the use context can assume
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/// "amdgpu-ieee"="true" and KnownIEEEMode::Off if we can assume
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/// "amdgpu-ieee"="false".
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KnownIEEEMode fpenvIEEEMode(const Instruction &I) const;
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/// Account for loads of i8 vector types to have reduced cost. For
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/// example the cost of load 4 i8s values is one is the cost of loading
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/// a single i32 value.
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InstructionCost getMemoryOpCost(
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unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
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const Instruction *I = nullptr) const override;
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/// When counting parts on AMD GPUs, account for i8s being grouped
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/// together under a single i32 value. Otherwise fall back to base
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/// implementation.
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unsigned getNumberOfParts(Type *Tp) const override;
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InstructionUniformity getInstructionUniformity(const Value *V) const override;
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InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
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StackOffset BaseOffset, bool HasBaseReg,
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int64_t Scale,
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unsigned AddrSpace) const override;
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bool isLSRCostLess(const TTI::LSRCost &A,
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const TTI::LSRCost &B) const override;
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bool isNumRegsMajorCostOfLSR() const override;
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bool shouldDropLSRSolutionIfLessProfitable() const override;
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bool isUniform(const Instruction *I,
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const SmallBitVector &UniformArgs) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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