ade43a54d4
Initial support for acquire-release atomics, specified as part of https://github.com/WebAssembly/shared-everything-threads This adds an ordering operand to atomic loads, stores, RMWs, wait/notify, and fences. It currently defaults to 0 and ISel is not updated yet, so atomics produced by the compiler will still always be seqcst. Asm parsing and printing, binary emission and disassembly are all updated. Binary emission will always use the old encoding because the encoding is smaller, and to get backwards compatibility for free.
70 lines
2.8 KiB
C++
70 lines
2.8 KiB
C++
// WebAssemblyInstPrinter.h - Print wasm MCInst to assembly syntax -*- C++ -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This class prints an WebAssembly MCInst to wasm file syntax.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_INSTPRINTER_WEBASSEMBLYINSTPRINTER_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_INSTPRINTER_WEBASSEMBLYINSTPRINTER_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/BinaryFormat/Wasm.h"
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#include "llvm/CodeGenTypes/MachineValueType.h"
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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class MCSubtargetInfo;
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class WebAssemblyInstPrinter final : public MCInstPrinter {
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uint64_t ControlFlowCounter = 0;
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SmallVector<std::pair<uint64_t, bool>, 4> ControlFlowStack;
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SmallVector<uint64_t, 4> TryStack;
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enum EHInstKind { TRY, CATCH_LEGACY, CATCH_ALL_LEGACY };
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SmallVector<EHInstKind, 4> EHInstStack;
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public:
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WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI);
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void printRegName(raw_ostream &OS, MCRegister Reg) override;
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void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
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const MCSubtargetInfo &STI, raw_ostream &OS) override;
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// Used by tblegen code.
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void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O, bool IsVariadicDef = false);
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void printBrList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printWebAssemblyP2AlignOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printWebAssemblyMemOrderOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printWebAssemblySignatureOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printCatchList(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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// Autogenerated by tblgen.
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std::pair<const char *, uint64_t>
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getMnemonic(const MCInst &MI) const override;
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void printInstruction(const MCInst *MI, uint64_t Address,
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const MCSubtargetInfo &STI, raw_ostream &O);
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static const char *getRegisterName(MCRegister Reg);
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};
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} // end namespace llvm
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#endif
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