3a1d5b5b8c
Which is under discussion in https://github.com/llvm/llvm-project/issues/179036. x86-64 support is added in https://github.com/llvm/llvm-project/pull/180242. Now add x86-32 support for reserving EDI via `-ffixed-edi` Update the X86 backend to respect those reservations in register handling, callee-save logic, and memcpy/memset lowering, and add driver/codegen tests. Add clang driver support for -ffixed-edi and map it to the reserve-edi target feature on i386. Teach the X86 backend to treat EDI as a user-reserved register in register lookup, reserved-register tracking, and callee-save handling, and avoid selecting REP MOVS/REP STOS when EDI is reserved. Add driver, Sema, and codegen tests covering option handling, named global register variables, and the resulting code generation changes. Signed-off-by: ZhouGuangyuan <zhouguangyuan.xian@gmail.com>
419 lines
16 KiB
C++
419 lines
16 KiB
C++
//===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86SelectionDAGInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86SelectionDAGInfo.h"
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#include "X86InstrInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#define GET_SDNODE_DESC
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#include "X86GenSDNodeInfo.inc"
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using namespace llvm;
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#define DEBUG_TYPE "x86-selectiondag-info"
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static cl::opt<bool>
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UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false),
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cl::desc("Use fast short rep mov in memcpy lowering"));
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X86SelectionDAGInfo::X86SelectionDAGInfo()
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: SelectionDAGGenTargetInfo(X86GenSDNodeInfo) {}
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const char *X86SelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
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#define NODE_NAME_CASE(NODE) \
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case X86ISD::NODE: \
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return "X86ISD::" #NODE;
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// These nodes don't have corresponding entries in *.td files yet.
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switch (static_cast<X86ISD::NodeType>(Opcode)) {
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NODE_NAME_CASE(POP_FROM_X87_REG)
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NODE_NAME_CASE(GlobalBaseReg)
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NODE_NAME_CASE(LCMPXCHG16_SAVE_RBX_DAG)
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NODE_NAME_CASE(PCMPESTR)
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NODE_NAME_CASE(PCMPISTR)
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NODE_NAME_CASE(MGATHER)
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NODE_NAME_CASE(MSCATTER)
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NODE_NAME_CASE(AESENCWIDE128KL)
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NODE_NAME_CASE(AESDECWIDE128KL)
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NODE_NAME_CASE(AESENCWIDE256KL)
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NODE_NAME_CASE(AESDECWIDE256KL)
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}
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#undef NODE_NAME_CASE
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return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
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}
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bool X86SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
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// These nodes don't have corresponding entries in *.td files yet.
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if (Opcode >= X86ISD::FIRST_MEMORY_OPCODE &&
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Opcode <= X86ISD::LAST_MEMORY_OPCODE)
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return true;
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return SelectionDAGGenTargetInfo::isTargetMemoryOpcode(Opcode);
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}
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void X86SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
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const SDNode *N) const {
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switch (N->getOpcode()) {
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default:
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break;
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case X86ISD::VP2INTERSECT:
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// invalid number of results; expected 1, got 2
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case X86ISD::FSETCCM_SAE:
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// invalid number of operands; expected 3, got 4
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case X86ISD::CVTTP2SI_SAE:
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case X86ISD::CVTTP2UI_SAE:
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case X86ISD::CVTTP2IBS_SAE:
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// invalid number of operands; expected 1, got 2
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case X86ISD::CMPMM_SAE:
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// invalid number of operands; expected 4, got 5
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case X86ISD::CALL:
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case X86ISD::NT_BRIND:
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// operand #1 must have type i32 (iPTR), but has type i64
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case X86ISD::INSERTQI:
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case X86ISD::EXTRQI:
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// result #0 must have type v2i64, but has type v16i8/v8i16
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return;
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}
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SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
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}
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/// Returns the best type to use with repmovs/repstos depending on alignment.
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static MVT getOptimalRepType(const X86Subtarget &Subtarget, Align Alignment) {
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uint64_t Align = Alignment.value();
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assert((Align != 0) && "Align is normalized");
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assert(isPowerOf2_64(Align) && "Align is a power of 2");
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switch (Align) {
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case 1:
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return MVT::i8;
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case 2:
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return MVT::i16;
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case 4:
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return MVT::i32;
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default:
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return Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
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}
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}
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bool X86SelectionDAGInfo::isBaseRegConflictPossible(
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SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
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// We cannot use TRI->hasBasePointer() until *after* we select all basic
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// blocks. Legalization may introduce new stack temporaries with large
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// alignment requirements. Fall back to generic code if there are any
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// dynamic stack adjustments (hopefully rare) and the base pointer would
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// conflict if we had to use it.
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MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
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if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
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return false;
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const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
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DAG.getSubtarget().getRegisterInfo());
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return llvm::is_contained(ClobberSet, TRI->getBaseRegister());
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}
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/// Emit a single REP STOSB instruction for a particular constant size.
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static SDValue emitRepstos(const X86Subtarget &Subtarget, SelectionDAG &DAG,
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const SDLoc &dl, SDValue Chain, SDValue Dst,
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SDValue Val, SDValue Size, MVT AVT) {
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const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
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unsigned AX = X86::AL;
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switch (AVT.getSizeInBits()) {
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case 8:
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AX = X86::AL;
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break;
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case 16:
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AX = X86::AX;
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break;
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case 32:
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AX = X86::EAX;
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break;
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default:
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AX = X86::RAX;
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break;
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}
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const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX;
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const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
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SDValue InGlue;
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Chain = DAG.getCopyToReg(Chain, dl, AX, Val, InGlue);
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InGlue = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, CX, Size, InGlue);
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InGlue = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, DI, Dst, InGlue);
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InGlue = Chain.getValue(1);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = {Chain, DAG.getValueType(AVT), InGlue};
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return DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
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}
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/// Emit a single REP STOSB instruction for a particular constant size.
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static SDValue emitRepstosB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
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const SDLoc &dl, SDValue Chain, SDValue Dst,
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SDValue Val, uint64_t Size) {
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return emitRepstos(Subtarget, DAG, dl, Chain, Dst, Val,
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DAG.getIntPtrConstant(Size, dl), MVT::i8);
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}
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/// Returns a REP STOS instruction, possibly with a few load/stores to implement
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/// a constant size memory set. In some cases where we know REP MOVS is
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/// inefficient we return an empty SDValue so the calling code can either
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/// generate a store sequence or call the runtime memset function.
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static SDValue emitConstantSizeRepstos(SelectionDAG &DAG,
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const X86Subtarget &Subtarget,
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const SDLoc &dl, SDValue Chain,
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SDValue Dst, SDValue Val, uint64_t Size,
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EVT SizeVT, Align Alignment,
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bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo) {
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/// In case we optimize for size, we use repstosb even if it's less efficient
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/// so we can save the loads/stores of the leftover.
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if (DAG.getMachineFunction().getFunction().hasMinSize()) {
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if (auto *ValC = dyn_cast<ConstantSDNode>(Val)) {
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// Special case 0 because otherwise we get large literals,
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// which causes larger encoding.
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if ((Size & 31) == 0 && (ValC->getZExtValue() & 255) == 0) {
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MVT BlockType = MVT::i32;
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const uint64_t BlockBits = BlockType.getSizeInBits();
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const uint64_t BlockBytes = BlockBits / 8;
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const uint64_t BlockCount = Size / BlockBytes;
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Val = DAG.getConstant(0, dl, BlockType);
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// repstosd is same size as repstosb
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return emitRepstos(Subtarget, DAG, dl, Chain, Dst, Val,
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DAG.getIntPtrConstant(BlockCount, dl), BlockType);
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}
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}
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return emitRepstosB(Subtarget, DAG, dl, Chain, Dst, Val, Size);
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}
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if (Size > Subtarget.getMaxInlineSizeThreshold())
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return SDValue();
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// If not DWORD aligned or size is more than the threshold, call the library.
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// The libc version is likely to be faster for these cases. It can use the
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// address value and run time information about the CPU.
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if (Alignment < Align(4))
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return SDValue();
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MVT BlockType = MVT::i8;
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uint64_t BlockCount = Size;
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uint64_t BytesLeft = 0;
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SDValue OriginalVal = Val;
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if (auto *ValC = dyn_cast<ConstantSDNode>(Val)) {
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BlockType = getOptimalRepType(Subtarget, Alignment);
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uint64_t Value = ValC->getZExtValue() & 255;
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const uint64_t BlockBits = BlockType.getSizeInBits();
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if (BlockBits >= 16)
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Value = (Value << 8) | Value;
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if (BlockBits >= 32)
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Value = (Value << 16) | Value;
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if (BlockBits >= 64)
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Value = (Value << 32) | Value;
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const uint64_t BlockBytes = BlockBits / 8;
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BlockCount = Size / BlockBytes;
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BytesLeft = Size % BlockBytes;
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Val = DAG.getConstant(Value, dl, BlockType);
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}
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SDValue RepStos =
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emitRepstos(Subtarget, DAG, dl, Chain, Dst, Val,
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DAG.getIntPtrConstant(BlockCount, dl), BlockType);
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/// RepStos can process the whole length.
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if (BytesLeft == 0)
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return RepStos;
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// Handle the last 1 - 7 bytes.
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SmallVector<SDValue, 4> Results;
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Results.push_back(RepStos);
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unsigned Offset = Size - BytesLeft;
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EVT AddrVT = Dst.getValueType();
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Results.push_back(
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DAG.getMemset(Chain, dl,
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DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
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DAG.getConstant(Offset, dl, AddrVT)),
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OriginalVal, DAG.getConstant(BytesLeft, dl, SizeVT),
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Alignment, isVolatile, AlwaysInline,
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/* CI */ nullptr, DstPtrInfo.getWithOffset(Offset)));
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
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}
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SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
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SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
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SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo) const {
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const X86Subtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<X86Subtarget>();
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// If to a segment-relative address space, use the default lowering.
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if (DstPtrInfo.getAddrSpace() >= 256)
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return SDValue();
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// REP STOS uses EDI on x86-32. Fall back if the user reserved EDI, so the
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// generic expander can avoid emitting REP STOS.
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if (!Subtarget.is64Bit() && Subtarget.isRegisterReservedByUser(X86::EDI))
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return SDValue();
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// If the base register might conflict with our physical registers, bail out.
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const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
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X86::ECX, X86::EAX, X86::EDI};
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if (isBaseRegConflictPossible(DAG, ClobberSet))
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return SDValue();
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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if (!ConstantSize)
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return SDValue();
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return emitConstantSizeRepstos(
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DAG, Subtarget, dl, Chain, Dst, Val, ConstantSize->getZExtValue(),
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Size.getValueType(), Alignment, isVolatile, AlwaysInline, DstPtrInfo);
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}
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/// Emit a single REP MOVS{B,W,D,Q} instruction.
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static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG,
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const SDLoc &dl, SDValue Chain, SDValue Dst,
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SDValue Src, SDValue Size, MVT AVT) {
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const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
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const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX;
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const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
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const unsigned SI = Use64BitRegs ? X86::RSI : X86::ESI;
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SDValue InGlue;
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Chain = DAG.getCopyToReg(Chain, dl, CX, Size, InGlue);
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InGlue = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, DI, Dst, InGlue);
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InGlue = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, SI, Src, InGlue);
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InGlue = Chain.getValue(1);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = {Chain, DAG.getValueType(AVT), InGlue};
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return DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
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}
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/// Emit a single REP MOVSB instruction for a particular constant size.
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static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
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const SDLoc &dl, SDValue Chain, SDValue Dst,
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SDValue Src, uint64_t Size) {
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return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
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DAG.getIntPtrConstant(Size, dl), MVT::i8);
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}
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/// Returns a REP MOVS instruction, possibly with a few load/stores to implement
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/// a constant size memory copy. In some cases where we know REP MOVS is
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/// inefficient we return an empty SDValue so the calling code can either
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/// generate a load/store sequence or call the runtime memcpy function.
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static SDValue emitConstantSizeRepmov(
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SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl,
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SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT,
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Align Alignment, bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) {
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/// In case we optimize for size, we use repmovsb even if it's less efficient
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/// so we can save the loads/stores of the leftover.
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
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/// TODO: Revisit next line: big copy with ERMSB on march >= haswell are very
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/// efficient.
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if (!AlwaysInline && Size > Subtarget.getMaxInlineSizeThreshold())
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return SDValue();
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/// If we have enhanced repmovs we use it.
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if (Subtarget.hasERMSB())
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return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
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assert(!Subtarget.hasERMSB() && "No efficient RepMovs");
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/// We assume runtime memcpy will do a better job for unaligned copies when
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/// ERMS is not present.
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if (!AlwaysInline && (Alignment < Align(4)))
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return SDValue();
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const MVT BlockType = getOptimalRepType(Subtarget, Alignment);
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const uint64_t BlockBytes = BlockType.getSizeInBits() / 8;
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const uint64_t BlockCount = Size / BlockBytes;
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const uint64_t BytesLeft = Size % BlockBytes;
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SDValue RepMovs =
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emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
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DAG.getIntPtrConstant(BlockCount, dl), BlockType);
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/// RepMov can process the whole length.
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if (BytesLeft == 0)
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return RepMovs;
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assert(BytesLeft && "We have leftover at this point");
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// Handle the last 1 - 7 bytes.
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SmallVector<SDValue, 4> Results;
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Results.push_back(RepMovs);
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unsigned Offset = Size - BytesLeft;
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EVT DstVT = Dst.getValueType();
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EVT SrcVT = Src.getValueType();
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Results.push_back(DAG.getMemcpy(
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Chain, dl,
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DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
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DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
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DAG.getConstant(BytesLeft, dl, SizeVT), Alignment, isVolatile,
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/*AlwaysInline*/ true, /*CI=*/nullptr, std::nullopt,
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DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset)));
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
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}
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SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
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SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
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const X86Subtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<X86Subtarget>();
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// If to a segment-relative address space, use the default lowering.
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if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256)
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return SDValue();
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// REP MOVS uses EDI/ESI on x86-32. fall back only when EDI is
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// reserved so the generic expander can avoid emitting REP MOVS.
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if (!Subtarget.is64Bit() && Subtarget.isRegisterReservedByUser(X86::EDI))
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return SDValue();
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// If the base registers conflict with our physical registers, use the default
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// lowering.
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const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
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X86::ECX, X86::ESI, X86::EDI};
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if (isBaseRegConflictPossible(DAG, ClobberSet))
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return SDValue();
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// If enabled and available, use fast short rep mov.
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if (UseFSRMForMemcpy && Subtarget.hasFSRM())
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return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8);
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/// Handle constant sizes
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if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size))
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return emitConstantSizeRepmov(DAG, Subtarget, dl, Chain, Dst, Src,
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ConstantSize->getZExtValue(),
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Size.getValueType(), Alignment, isVolatile,
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AlwaysInline, DstPtrInfo, SrcPtrInfo);
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return SDValue();
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}
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