5734d978d0
Revised #166962. This patch aims to fix the original compile time regression by restricting the optimisation to run only on non-constant splats. Without the guard, an infinite loop is caused because the `CONCAT(SCALAR_TO_VECTOR, zero)` folds back into the same `BUILD_VECTOR` and immediately re-enters `LowerBUILD_VECTOR`. This patch was tested with the original TensorFlow reproduction provided on the PR and shows a (very) slight improvement on compile-time.
218 lines
8.4 KiB
LLVM
218 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
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declare <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float>) #2
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declare <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8>, <8 x i8>) #2
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define <8 x half> @test1(<4 x float> noundef %a) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%vcvt_f16_f321.i = tail call <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float> %a)
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%0 = bitcast <4 x i16> %vcvt_f16_f321.i to <4 x half>
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%shuffle.i = shufflevector <4 x half> %0, <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x half> %shuffle.i
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}
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define <8 x i8> @test2(ptr nocapture noundef readonly %in, <8 x i8> noundef %idx) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr q1, [x0]
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; CHECK-NEXT: shrn v1.8b, v1.8h, #4
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; CHECK-NEXT: tbl v0.8b, { v1.16b }, v0.8b
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; CHECK-NEXT: ret
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entry:
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%0 = load <8 x i16>, ptr %in, align 2
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%1 = lshr <8 x i16> %0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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%vshrn_n = trunc <8 x i16> %1 to <8 x i8>
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%vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)
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ret <8 x i8> %vtbl11.i
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}
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define <8 x i8> @tbl1v8i8(ptr nocapture noundef readonly %in, <8 x i8> noundef %idx) {
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; CHECK-LABEL: tbl1v8i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr q1, [x0]
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; CHECK-NEXT: shrn v1.8b, v1.8h, #4
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; CHECK-NEXT: tbl v0.8b, { v1.16b }, v0.8b
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; CHECK-NEXT: ret
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entry:
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%0 = load <8 x i16>, ptr %in, align 2
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%1 = lshr <8 x i16> %0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
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%vshrn_n = trunc <8 x i16> %1 to <8 x i8>
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%vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)
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ret <8 x i8> %vtbl11.i
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}
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define <8 x i16> @addpv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
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; CHECK-LABEL: addpv4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: addp v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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entry:
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%vpadd_v2.i = tail call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %a, <4 x i16> %b)
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%shuffle.i = shufflevector <4 x i16> %vpadd_v2.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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define <8 x i16> @addv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
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; CHECK-LABEL: addv4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: ret
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entry:
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%add.i = add <4 x i16> %b, %a
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%shuffle.i = shufflevector <4 x i16> %add.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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define <16 x i8> @rshrn(<8 x i16> noundef %a, <4 x i16> noundef %b) {
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; CHECK-LABEL: rshrn:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rshrn v0.8b, v0.8h, #3
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; CHECK-NEXT: ret
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entry:
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%vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a, i32 3)
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%shuffle.i = shufflevector <8 x i8> %vrshrn_n1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <16 x i8> @tbl1(<16 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: tbl1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b
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; CHECK-NEXT: ret
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entry:
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%vtbl11 = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
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%shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <2 x double> @fadd(double noundef %x, double noundef %y) {
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; CHECK-LABEL: fadd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fadd d0, d0, d1
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; CHECK-NEXT: ret
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entry:
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%add = fadd double %x, %y
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%vecinit1 = insertelement <2 x double> poison, double %add, i64 0
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%vecinit2 = insertelement <2 x double> %vecinit1, double 0.0, i64 1
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ret <2 x double> %vecinit2
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}
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define <16 x i8> @bsl(<4 x i16> noundef %a, <4 x i16> noundef %c, <4 x i16> noundef %d, <4 x i16> noundef %b) {
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; CHECK-LABEL: bsl:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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entry:
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%vbsl3.i = and <4 x i16> %c, %a
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%0 = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
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%vbsl4.i = and <4 x i16> %0, %d
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%vbsl5.i = or <4 x i16> %vbsl4.i, %vbsl3.i
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%1 = bitcast <4 x i16> %vbsl5.i to <8 x i8>
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%shuffle.i = shufflevector <8 x i8> %1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <16 x i8> @load(ptr %a, <8 x i8> %b) {
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; CHECK-LABEL: load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ret
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entry:
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%vtbl11 = load <8 x i8>, ptr %a
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%shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <16 x i8> @insertzero_v8i8(<8 x i8> %a) {
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; CHECK-LABEL: insertzero_v8i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i
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}
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define <8 x i16> @insertzero_v4i16(<4 x i16> %a) {
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; CHECK-LABEL: insertzero_v4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <4 x i16> %a, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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define <4 x i32> @insertzero_v2i32(<2 x i32> %a) {
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; CHECK-LABEL: insertzero_v2i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <2 x i32> %a, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %shuffle.i
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}
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define <2 x i64> @insertzero_v1i64(<1 x i64> %a) {
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; CHECK-LABEL: insertzero_v1i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <1 x i64> %a, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>
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ret <2 x i64> %shuffle.i
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}
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define <8 x half> @insertzero_v4f16(<4 x half> %a) {
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; CHECK-LABEL: insertzero_v4f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x half> %shuffle.i
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}
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define <8 x bfloat> @insertzero_v4bf16(<4 x bfloat> %a) {
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; CHECK-LABEL: insertzero_v4bf16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <4 x bfloat> %a, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x bfloat> %shuffle.i
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}
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define <4 x float> @insertzero_v2f32(<2 x float> %a) {
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; CHECK-LABEL: insertzero_v2f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <2 x float> %a, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x float> %shuffle.i
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}
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define <2 x double> @insertzero_v1f64(<1 x double> %a) {
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; CHECK-LABEL: insertzero_v1f64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d0, d0
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; CHECK-NEXT: ret
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entry:
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%shuffle.i = shufflevector <1 x double> %a, <1 x double> zeroinitializer, <2 x i32> <i32 0, i32 1>
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ret <2 x double> %shuffle.i
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}
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declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
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declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)
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