ad1a45b903
Currently, when SDAG is run on AArch64 and an `optnone` function is encountered, the selector is chosen as FastISel. AArch64 makes use of GlobalISel at O0 and this patch aims to align `optnone` with this functionality. A flag is exposed to enable this functionality for a given backend but, as AArch64 is currently the only backend I could find using GlobalISel at O0 this is the only one with it implemented. This flag is set when the target supports GlobalISel & GlobalISel hasn't been forced by the user, the target machine or by being at an optimisation level lower than `EnableGlobalISelAtO`. If this happens, the GlobalISel passes are included as shown in `llvm/test/CodeGen/AArch64/O3-pipeline.ll` and skipped by IRTranslator for functions not marked as `optnone`. In updating the tests based on this functionality, I found some unused check lines or run lines that mixed SDAG with GlobalISel pass names which have been fixed. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
77 lines
3.4 KiB
LLVM
77 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=aarch64-isel < %s | FileCheck %s
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declare void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float>, <4 x float>, ptr)
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declare void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, ptr)
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declare void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, <4 x float>, ptr)
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declare void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float>, <4 x float>, ptr)
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declare void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, ptr)
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declare void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, <4 x float>, ptr)
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declare void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float>, <4 x float>, i64, ptr)
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declare void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, i64, ptr)
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declare void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, ptr)
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define void @addstx(ptr %res, ptr %a, ptr %b, ptr %c, ptr %d) {
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%al = load <4 x float>, ptr %a
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%bl = load <4 x float>, ptr %b
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%cl = load <4 x float>, ptr %c
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%dl = load <4 x float>, ptr %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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tail call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> %ar, <4 x float> %br, ptr %res)
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; CHECK: ST2Twov4s {{.*}} :: (store (s256) {{.*}})
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tail call void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, ptr %res)
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; CHECK: ST3Threev4s {{.*}} :: (store (s384) {{.*}})
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tail call void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, ptr %res)
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; CHECK: ST4Fourv4s {{.*}} :: (store (s512) {{.*}})
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ret void
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}
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define void @addst1x(ptr %res, ptr %a, ptr %b, ptr %c, ptr %d) {
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%al = load <4 x float>, ptr %a
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%bl = load <4 x float>, ptr %b
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%cl = load <4 x float>, ptr %c
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%dl = load <4 x float>, ptr %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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tail call void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float> %ar, <4 x float> %br, ptr %res)
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; CHECK: ST1Twov4s {{.*}} :: (store (s256) {{.*}})
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tail call void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, ptr %res)
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; CHECK: ST1Threev4s {{.*}} :: (store (s384) {{.*}})
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tail call void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, ptr %res)
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; CHECK: ST1Fourv4s {{.*}} :: (store (s512) {{.*}})
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ret void
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}
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define void @addstxlane(ptr %res, ptr %a, ptr %b, ptr %c, ptr %d) {
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%al = load <4 x float>, ptr %a
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%bl = load <4 x float>, ptr %b
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%cl = load <4 x float>, ptr %c
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%dl = load <4 x float>, ptr %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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tail call void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float> %ar, <4 x float> %br, i64 1, ptr %res)
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; CHECK: ST2i32 {{.*}} :: (store (s64) {{.*}})
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tail call void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, ptr %res)
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; CHECK: ST3i32 {{.*}} :: (store (s96) {{.*}})
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tail call void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, ptr %res)
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; CHECK: ST4i32 {{.*}} :: (store (s128) {{.*}})
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ret void
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}
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