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llvm-project/llvm/test/CodeGen/AArch64/vec-libcalls.ll
Shubham Sandeep Rastogi 44b94a4f75
[AArch64][DebugInfo]Add Target hooks for InstrRef on AArch64 (#165953) 
This patch adds the target hooks required by Instruction Referencing for
the AArch64 target, as mentioned in
https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks

Which allows the Instruction Referenced LiveDebugValues Pass to track
spills and restore instructions.

With this patch we can use the
`llvm/utils/llvm-locstats/llvm-locstats.py` to see the coverage
statistics on a clang.dSYM built with in RelWithDebInfo we can see:

coverage with dbg_value:
```
=================================================
            Debug Location Statistics       
 =================================================
     cov%           samples         percentage(~)  
 -------------------------------------------------
   0%              5828021               38%
   (0%,10%)         127739                0%
   [10%,20%)        143344                0%
   [20%,30%)        172100                1%
   [30%,40%)        193173                1%
   [40%,50%)        127366                0%
   [50%,60%)        308350                2%
   [60%,70%)        257055                1%
   [70%,80%)        212410                1%
   [80%,90%)        295316                1%
   [90%,100%)       349280                2%
   100%            7313157               47%
 =================================================
 -the number of debug variables processed: 15327311
 -PC ranges covered: 67%
 -------------------------------------------------
 -total availability: 62%
 =================================================
 ```
 
coverage with InstrRef without target hooks fix:
```
 =================================================
            Debug Location Statistics       
 =================================================
     cov%           samples         percentage(~)  
 -------------------------------------------------
   0%              6052807               39%
   (0%,10%)         127710                0%
   [10%,20%)        129999                0%
   [20%,30%)        155011                1%
   [30%,40%)        171206                1%
   [40%,50%)        102861                0%
   [50%,60%)        264734                1%
   [60%,70%)        212386                1%
   [70%,80%)        176872                1%
   [80%,90%)        242120                1%
   [90%,100%)       254465                1%
   100%            7437215               48%
 =================================================
 -the number of debug variables processed: 15327386
 -PC ranges covered: 67%
 -------------------------------------------------
 -total availability: 60%
 =================================================
 ```
 
coverage with InstrRef with target hooks fix:
```
 =================================================
            Debug Location Statistics       
 =================================================
     cov%           samples         percentage(~)  
 -------------------------------------------------
   0%              5972267               39%
   (0%,10%)         118873                0%
   [10%,20%)        127138                0%
   [20%,30%)        153181                1%
   [30%,40%)        170102                1%
   [40%,50%)        102180                0%
   [50%,60%)        263672                1%
   [60%,70%)        212865                1%
   [70%,80%)        176633                1%
   [80%,90%)        242403                1%
   [90%,100%)       264441                1%
   100%            7494527               48%
 =================================================
 -the number of debug variables processed: 15298282
 -PC ranges covered: 71%
 -------------------------------------------------
 -total availability: 61%
 =================================================
 ```
 
 I believe this should be a good indication that Instruction Referencing should be turned on for AArch64?
2025-11-14 10:36:47 -08:00

776 lines
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
; PR38527 - https://bugs.llvm.org/show_bug.cgi?id=38527
; Use fsin as the representative test for various data types.
declare <1 x float> @llvm.sin.v1f32(<1 x float>)
declare <2 x float> @llvm.sin.v2f32(<2 x float>)
declare <3 x float> @llvm.sin.v3f32(<3 x float>)
declare <4 x float> @llvm.sin.v4f32(<4 x float>)
declare <5 x float> @llvm.sin.v5f32(<5 x float>)
declare <6 x float> @llvm.sin.v6f32(<6 x float>)
declare <3 x double> @llvm.sin.v3f64(<3 x double>)
; Verify that all of the potential libcall candidates are handled.
; Some of these have custom lowering, so those cases won't have
; libcalls.
declare <3 x float> @llvm.fabs.v3f32(<3 x float>)
declare <3 x float> @llvm.ceil.v3f32(<3 x float>)
declare <3 x float> @llvm.cos.v3f32(<3 x float>)
declare <3 x float> @llvm.tan.v3f32(<3 x float>)
declare <3 x float> @llvm.asin.v3f32(<3 x float>)
declare <3 x float> @llvm.acos.v3f32(<3 x float>)
declare <3 x float> @llvm.atan.v3f32(<3 x float>)
declare <3 x float> @llvm.atan2.v3f32(<3 x float>, <3 x float>)
declare <3 x float> @llvm.sinh.v3f32(<3 x float>)
declare <3 x float> @llvm.cosh.v3f32(<3 x float>)
declare <3 x float> @llvm.tanh.v3f32(<3 x float>)
declare <3 x float> @llvm.exp.v3f32(<3 x float>)
declare <3 x float> @llvm.exp2.v3f32(<3 x float>)
declare <3 x float> @llvm.floor.v3f32(<3 x float>)
declare <3 x float> @llvm.log.v3f32(<3 x float>)
declare <3 x float> @llvm.log10.v3f32(<3 x float>)
declare <3 x float> @llvm.log2.v3f32(<3 x float>)
declare <3 x float> @llvm.nearbyint.v3f32(<3 x float>)
declare <3 x float> @llvm.rint.v3f32(<3 x float>)
declare <3 x float> @llvm.round.v3f32(<3 x float>)
declare <3 x float> @llvm.roundeven.v3f32(<3 x float>)
declare <3 x float> @llvm.sqrt.v3f32(<3 x float>)
declare <3 x float> @llvm.trunc.v3f32(<3 x float>)
define <1 x float> @sin_v1f32(<1 x float> %x) nounwind {
; CHECK-LABEL: sin_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%r = call <1 x float> @llvm.sin.v1f32(<1 x float> %x)
ret <1 x float> %r
}
define <2 x float> @sin_v2f32(<2 x float> %x) nounwind {
; CHECK-LABEL: sin_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl sinf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <2 x float> @llvm.sin.v2f32(<2 x float> %x)
ret <2 x float> %r
}
define <3 x float> @sin_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: sin_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl sinf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.sin.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <4 x float> @sin_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: sin_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl sinf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[3]
; CHECK-NEXT: str q1, [sp] // 16-byte Spill
; CHECK-NEXT: bl sinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[3], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <4 x float> @llvm.sin.v4f32(<4 x float> %x)
ret <4 x float> %r
}
define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
; CHECK-LABEL: sin_v5f32:
; CHECK: // %bb.0:
; CHECK-NEXT: str d12, [sp, #-48]! // 8-byte Folded Spill
; CHECK-NEXT: stp d11, d10, [sp, #8] // 16-byte Folded Spill
; CHECK-NEXT: fmov s10, s2
; CHECK-NEXT: fmov s11, s1
; CHECK-NEXT: stp d9, d8, [sp, #24] // 16-byte Folded Spill
; CHECK-NEXT: fmov s8, s4
; CHECK-NEXT: fmov s9, s3
; CHECK-NEXT: str x30, [sp, #40] // 8-byte Spill
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s12, s0
; CHECK-NEXT: fmov s0, s11
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s11, s0
; CHECK-NEXT: fmov s0, s10
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s10, s0
; CHECK-NEXT: fmov s0, s9
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s9, s0
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s1, s11
; CHECK-NEXT: fmov s2, s10
; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Reload
; CHECK-NEXT: fmov s3, s9
; CHECK-NEXT: ldp d9, d8, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: ldp d11, d10, [sp, #8] // 16-byte Folded Reload
; CHECK-NEXT: fmov s4, s0
; CHECK-NEXT: fmov s0, s12
; CHECK-NEXT: ldr d12, [sp], #48 // 8-byte Folded Reload
; CHECK-NEXT: ret
%r = call <5 x float> @llvm.sin.v5f32(<5 x float> %x)
ret <5 x float> %r
}
define <6 x float> @sin_v6f32(<6 x float> %x) nounwind {
; CHECK-LABEL: sin_v6f32:
; CHECK: // %bb.0:
; CHECK-NEXT: stp d13, d12, [sp, #-64]! // 16-byte Folded Spill
; CHECK-NEXT: stp d11, d10, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: fmov s10, s3
; CHECK-NEXT: fmov s11, s2
; CHECK-NEXT: stp d9, d8, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: fmov s8, s5
; CHECK-NEXT: fmov s9, s4
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill
; CHECK-NEXT: fmov s12, s1
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s13, s0
; CHECK-NEXT: fmov s0, s12
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s12, s0
; CHECK-NEXT: fmov s0, s11
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s11, s0
; CHECK-NEXT: fmov s0, s10
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s10, s0
; CHECK-NEXT: fmov s0, s9
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s9, s0
; CHECK-NEXT: fmov s0, s8
; CHECK-NEXT: bl sinf
; CHECK-NEXT: fmov s2, s11
; CHECK-NEXT: fmov s3, s10
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload
; CHECK-NEXT: fmov s4, s9
; CHECK-NEXT: ldp d9, d8, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp d11, d10, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: fmov s5, s0
; CHECK-NEXT: fmov s0, s13
; CHECK-NEXT: fmov s1, s12
; CHECK-NEXT: ldp d13, d12, [sp], #64 // 16-byte Folded Reload
; CHECK-NEXT: ret
%r = call <6 x float> @llvm.sin.v6f32(<6 x float> %x)
ret <6 x float> %r
}
define <3 x double> @sin_v3f64(<3 x double> %x) nounwind {
; CHECK-LABEL: sin_v3f64:
; CHECK: // %bb.0:
; CHECK-NEXT: str d10, [sp, #-32]! // 8-byte Folded Spill
; CHECK-NEXT: stp d9, d8, [sp, #8] // 16-byte Folded Spill
; CHECK-NEXT: fmov d8, d2
; CHECK-NEXT: fmov d9, d1
; CHECK-NEXT: str x30, [sp, #24] // 8-byte Spill
; CHECK-NEXT: bl sin
; CHECK-NEXT: fmov d10, d0
; CHECK-NEXT: fmov d0, d9
; CHECK-NEXT: bl sin
; CHECK-NEXT: fmov d9, d0
; CHECK-NEXT: fmov d0, d8
; CHECK-NEXT: bl sin
; CHECK-NEXT: fmov d1, d9
; CHECK-NEXT: ldp d9, d8, [sp, #8] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #24] // 8-byte Reload
; CHECK-NEXT: fmov d2, d0
; CHECK-NEXT: fmov d0, d10
; CHECK-NEXT: ldr d10, [sp], #32 // 8-byte Folded Reload
; CHECK-NEXT: ret
%r = call <3 x double> @llvm.sin.v3f64(<3 x double> %x)
ret <3 x double> %r
}
define <3 x float> @fabs_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: fabs_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: fabs v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.fabs.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @ceil_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: ceil_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintp v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.ceil.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @cos_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: cos_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl cosf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl cosf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl cosf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.cos.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @tan_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: tan_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl tanf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl tanf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl tanf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.tan.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @asin_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: asin_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl asinf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl asinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl asinf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.asin.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @acos_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: acos_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl acosf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl acosf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl acosf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.acos.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @atan_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: atan_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl atanf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl atanf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl atanf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.atan.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @atan2_v3f32(<3 x float> %x, <3 x float> %y) nounwind {
; CHECK-LABEL: atan2_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64
; CHECK-NEXT: stp q0, q1, [sp, #16] // 32-byte Folded Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: mov s1, v1.s[1]
; CHECK-NEXT: str x30, [sp, #48] // 8-byte Spill
; CHECK-NEXT: bl atan2f
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldp q0, q1, [sp, #16] // 32-byte Folded Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: // kill: def $s1 killed $s1 killed $q1
; CHECK-NEXT: bl atan2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldp q0, q1, [sp, #16] // 32-byte Folded Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: mov s1, v1.s[2]
; CHECK-NEXT: bl atan2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #64
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.atan2.v3f32(<3 x float> %x, <3 x float> %y)
ret <3 x float> %r
}
define <3 x float> @sinh_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: sinh_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl sinhf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl sinhf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl sinhf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.sinh.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @cosh_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: cosh_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl coshf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl coshf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl coshf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.cosh.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @tanh_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: tanh_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl tanhf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl tanhf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl tanhf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.tanh.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @exp_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: exp_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl expf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl expf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl expf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.exp.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @exp2_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: exp2_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl exp2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.exp2.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @floor_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: floor_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintm v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.floor.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @log_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: log_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl logf
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl logf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl logf
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.log.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @log10_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: log10_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl log10f
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl log10f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl log10f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.log10.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @log2_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: log2_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT: mov s0, v0.s[1]
; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT: bl log2f
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bl log2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: mov v0.s[1], v1.s[0]
; CHECK-NEXT: str q0, [sp] // 16-byte Spill
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT: mov s0, v0.s[2]
; CHECK-NEXT: bl log2f
; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: mov v1.s[2], v0.s[0]
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.log2.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @nearbyint__v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: nearbyint__v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frinti v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.nearbyint.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @rint_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: rint_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.rint.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @round_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: round_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frinta v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.round.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @roundeven_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: roundeven_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintn v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.roundeven.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @sqrt_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: sqrt_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: fsqrt v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.sqrt.v3f32(<3 x float> %x)
ret <3 x float> %r
}
define <3 x float> @trunc_v3f32(<3 x float> %x) nounwind {
; CHECK-LABEL: trunc_v3f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintz v0.4s, v0.4s
; CHECK-NEXT: ret
%r = call <3 x float> @llvm.trunc.v3f32(<3 x float> %x)
ret <3 x float> %r
}
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