b8add3710d
Reasoning behind proposed change. This helps us move away from selecting
v_alignbits for fshr with uniform operands.
V_ALIGNBIT is defined in the ISA as:
D0.u32 = 32'U(({ S0.u32, S1.u32 } >> S2.u32[4 : 0]) & 0xffffffffLL)
Note: S0 carries the MSBs and S1 carries the LSBs of the value being
aligned.
I interpret that as : concat (s0, s1) >> S2, and use the 0X1F mask to
return the lower 32 bits.
fshr:
fshr i32 %src0, i32 %src1, i32 %src2
Where:
concat(%src0, %src1) represents the 64-bit value formed by %src0 as the
high 32 bits and %src1 as the low 32 bits.
%src2 is the shift amount.
Only the lower 32 bits are returned.
So these two are identical.
So, I can expand the V_ALIGNBIT through bit manipulation as:
Concat: S1 | (S0 << 32)
Shift: ((S1 | (S0 << 32)) >> S2)
Break the shift: (S1>>S2) | (S0 << (32 – S2)
The proposed pattern does exactly this.
Additionally, src2 in the fshr pattern should be:
* must be 0–31.
* If the shift is ≥32, hardware semantics differ; you must handle it
with extra instructions.
The extra S_ANDs limit the selection only to the last 5 bits
176 lines
7.3 KiB
LLVM
176 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GFX6 %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
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define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) %arg1) local_unnamed_addr #0 {
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; GFX6-LABEL: any_extend_vector_inreg_v16i8_to_v4i32:
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; GFX6: ; %bb.0: ; %bb
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; GFX6-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x9
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: v_mov_b32_e32 v0, 0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b32 s0, s14
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; GFX6-NEXT: s_mov_b32 s1, s15
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; GFX6-NEXT: s_load_dwordx8 s[4:11], s[12:13], 0x0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_load_dword s4, s[12:13], 0x8
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:13
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:15
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:14
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:8
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:11
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:10
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:4
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:6
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:1
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:3
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; GFX6-NEXT: s_lshr_b32 s7, s9, 16
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_lshl_b64 s[8:9], s[4:5], 8
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; GFX6-NEXT: s_waitcnt expcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s11
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:9
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; GFX6-NEXT: s_waitcnt expcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s5
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2
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; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
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; GFX6-NEXT: s_waitcnt expcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s9
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:12
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; GFX6-NEXT: s_lshr_b32 s5, s4, 8
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; GFX6-NEXT: s_lshr_b32 s4, s4, 24
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; GFX6-NEXT: s_waitcnt expcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s5
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:5
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; GFX6-NEXT: s_waitcnt expcnt(0)
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; GFX6-NEXT: v_mov_b32_e32 v0, s4
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; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:7
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: any_extend_vector_inreg_v16i8_to_v4i32:
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; GFX8: ; %bb.0: ; %bb
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; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
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; GFX8-NEXT: v_mov_b32_e32 v2, 0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_load_dword s0, s[8:9], 0x20
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; GFX8-NEXT: s_lshr_b32 s6, s5, 24
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; GFX8-NEXT: s_lshr_b32 s8, s2, 24
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 8
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; GFX8-NEXT: s_add_u32 s4, s10, 13
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 15
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 14
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 8
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 11
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 10
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 4
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 6
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 1
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: v_mov_b32_e32 v0, s10
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; GFX8-NEXT: v_mov_b32_e32 v1, s11
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; GFX8-NEXT: s_add_u32 s4, s10, 3
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: s_add_u32 s4, s10, 9
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: v_mov_b32_e32 v2, s7
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; GFX8-NEXT: s_add_u32 s4, s10, 2
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s5, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s4
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; GFX8-NEXT: v_mov_b32_e32 v1, s5
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; GFX8-NEXT: v_mov_b32_e32 v2, s1
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; GFX8-NEXT: s_add_u32 s0, s10, 5
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s1, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_mov_b32_e32 v2, s8
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; GFX8-NEXT: s_add_u32 s0, s10, 12
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s1, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_mov_b32_e32 v2, s3
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; GFX8-NEXT: s_add_u32 s0, s10, 7
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_addc_u32 s1, s11, 0
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_mov_b32_e32 v2, s6
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; GFX8-NEXT: flat_store_byte v[0:1], v2
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; GFX8-NEXT: s_endpgm
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bb:
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%tmp2 = load <16 x i8>, ptr addrspace(1) %arg, align 16
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%tmp3 = extractelement <16 x i8> %tmp2, i64 4
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%tmp6 = extractelement <16 x i8> %tmp2, i64 11
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%tmp10 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 2
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%tmp12 = load <16 x i8>, ptr addrspace(1) %tmp10, align 16
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%tmp13 = extractelement <16 x i8> %tmp12, i64 7
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%tmp17 = extractelement <16 x i8> %tmp12, i64 12
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%tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
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%tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
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%tmp24 = extractelement <16 x i8> %tmp23, i64 3
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%tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
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%tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
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%tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
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%tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5
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%tmp8 = insertelement <16 x i8> %tmp7, i8 0, i32 6
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%tmp9 = insertelement <16 x i8> %tmp8, i8 %tmp13, i32 7
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%tmp14 = insertelement <16 x i8> %tmp9, i8 0, i32 8
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%tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp17, i32 9
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%tmp16 = insertelement <16 x i8> %tmp15, i8 0, i32 10
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%tmp18 = insertelement <16 x i8> %tmp16, i8 0, i32 11
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%tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp24, i32 12
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store <16 x i8> %tmp19, ptr addrspace(1) %arg1, align 1
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ret void
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}
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attributes #0 = { nounwind }
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