65b576d2b0
Optimized IR will have worse performance when only a single lane is active. Disable optimizer when single lane is expected at compile time.
24 lines
1.1 KiB
LLVM
24 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12 %s
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; Check that no optimization is generated for single lane execution.
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define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace(8) %inout) "amdgpu-flat-work-group-size"="1,1" {
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; GFX12-LABEL: add_i32_constant:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
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; GFX12-NEXT: v_mov_b32_e32 v0, 5
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; GFX12-NEXT: v_mov_b32_e32 v1, 0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: buffer_atomic_add_u32 v0, off, s[0:3], null th:TH_ATOMIC_RETURN
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; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX12-NEXT: s_endpgm
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entry:
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%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
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store i32 %old, ptr addrspace(1) %out
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ret void
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}
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