67b6fd04dd
This fixes a regression exposed after 445415219708f9539801018e03282049ca33e0e2. This introduces a few small regressions for true16. There are more cases where the value can propagate through subregister extracts which need new handling. They're also small enough that perhaps there's a way to avoid needing to deal with this case in the first place.
268 lines
12 KiB
YAML
268 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass si-fold-operands -mattr=+real-true16 -o - %s | FileCheck %s
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---
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name: fold_16bit_subreg_1
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tracksRegLiveness: true
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registers:
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: fold_16bit_subreg_1
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; CHECK: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
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; CHECK-NEXT: [[V_CMP_EQ_F16_t16_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_EQ_F16_t16_e64 0, killed [[DEF1]], 2, [[DEF]].sub1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_t16_e64_]]
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:sgpr_lo16 = COPY %0.sub1_lo16:sreg_64_xexec
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%2:vgpr_16 = COPY %1:sgpr_lo16
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%3:vgpr_16 = IMPLICIT_DEF
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%4:sreg_32 = nofpexcept V_CMP_EQ_F16_t16_e64 0, killed %3:vgpr_16, 2, killed %2:vgpr_16, 0, 0, implicit $mode, implicit $exec
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S_ENDPGM 0, implicit %4
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...
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---
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name: fold_16bit_subreg_0
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tracksRegLiveness: true
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registers:
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: fold_16bit_subreg_0
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; CHECK: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
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; CHECK-NEXT: [[V_CMP_EQ_F16_t16_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_EQ_F16_t16_e64 0, killed [[DEF1]], 2, [[DEF]].sub0, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_t16_e64_]]
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%0:sreg_64_xexec = IMPLICIT_DEF
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%1:sgpr_lo16 = COPY %0.lo16:sreg_64_xexec
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%2:vgpr_16 = COPY %1:sgpr_lo16
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%3:vgpr_16 = IMPLICIT_DEF
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%4:sreg_32 = nofpexcept V_CMP_EQ_F16_t16_e64 0, killed %3:vgpr_16, 2, killed %2:vgpr_16, 0, 0, implicit $mode, implicit $exec
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S_ENDPGM 0, implicit %4
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...
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---
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name: sgpr_lo16
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tracksRegLiveness: true
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registers:
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: sgpr_lo16
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; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 30
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY [[S_MOV_B32_]]
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; CHECK-NEXT: [[V_ALIGNBIT_B32_t16_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_t16_e64 0, [[DEF]], 0, killed [[DEF1]], 0, killed [[COPY]], 0, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_t16_e64_]]
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%0:sreg_32 = IMPLICIT_DEF
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%1:sreg_32 = IMPLICIT_DEF
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%2:sreg_32 = S_MOV_B32 30
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%3:sgpr_lo16 = COPY %2.lo16:sreg_32
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%4:vgpr_16 = COPY %3:sgpr_lo16
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%5:vgpr_32 = V_ALIGNBIT_B32_t16_e64 0, %0:sreg_32, 0, killed %1:sreg_32, 0, killed %4:vgpr_16, 0, 0, implicit $exec
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S_ENDPGM 0, implicit %5
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...
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---
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name: fold_16bit_madmix_clamp
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tracksRegLiveness: true
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registers:
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: fold_16bit_madmix_clamp
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
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; CHECK-NEXT: [[V_FMA_MIXLO_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, [[COPY2]], 8, [[COPY1]], 0, [[COPY]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_16 = COPY [[V_FMA_MIXLO_F16_]]
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; CHECK-NEXT: $vgpr0 = COPY [[V_FMA_MIXLO_F16_]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
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%0:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr0
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%3:sreg_32 = IMPLICIT_DEF
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%4:vgpr_32 = COPY %3
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%5:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, %2, 8, %1, 0, %0, 0, %4, 0, 0, implicit $mode, implicit $exec
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%6:vgpr_16 = COPY %5
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%7:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %6, 0, %6, -1, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = COPY %7
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S_ENDPGM 0, implicit $vgpr0
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...
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---
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name: fold_16bit_subreg_1_clamp
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tracksRegLiveness: true
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registers:
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: fold_16bit_subreg_1_clamp
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
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; CHECK-NEXT: [[V_FMA_MIXLO_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, [[COPY2]], 8, [[COPY1]], 0, [[COPY]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, [[V_FMA_MIXLO_F16_]].lo16, 0, [[V_FMA_MIXLO_F16_]].lo16, -1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F16_t16_e64_]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
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%0:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr0
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%3:sreg_32 = IMPLICIT_DEF
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%4:vgpr_32 = COPY %3
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%5:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, %2, 8, %1, 0, %0, 0, %4, 0, 0, implicit $mode, implicit $exec
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%6:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %5.lo16, 0, %5.lo16, -1, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = COPY %6
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S_ENDPGM 0, implicit $vgpr0
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...
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---
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name: fold_16bit_subreg_2_clamp
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tracksRegLiveness: true
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registers:
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: fold_16bit_subreg_2_clamp
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
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; CHECK-NEXT: [[V_FMA_MIXLO_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, [[COPY2]], 8, [[COPY1]], 0, [[COPY]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, [[V_FMA_MIXLO_F16_]].lo16, 0, [[V_FMA_MIXLO_F16_]].lo16, -1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F16_t16_e64_]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
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%0:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr0
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%3:sreg_32 = IMPLICIT_DEF
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%4:vgpr_32 = COPY %3
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%5:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, %2, 8, %1, 0, %0, 0, %4, 0, 0, implicit $mode, implicit $exec
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%6:vgpr_16 = COPY %5.lo16
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%7:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %6, 0, %6, -1, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = COPY %7
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S_ENDPGM 0, implicit $vgpr0
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...
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---
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name: fold_16bit_phyreg_clamp
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tracksRegLiveness: true
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registers:
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: fold_16bit_phyreg_clamp
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
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; CHECK-NEXT: [[V_FMA_MIXLO_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, [[COPY2]], 8, [[COPY1]], 0, [[COPY]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: $vgpr10_lo16 = COPY [[V_FMA_MIXLO_F16_]]
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; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, $vgpr10_lo16, 0, $vgpr10_lo16, -1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F16_t16_e64_]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
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%0:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr0
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%3:sreg_32 = IMPLICIT_DEF
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%4:vgpr_32 = COPY %3
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%5:vgpr_32 = nofpexcept V_FMA_MIXLO_F16 8, %2, 8, %1, 0, %0, 0, %4, 0, 0, implicit $mode, implicit $exec
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$vgpr10_lo16 = COPY %5
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%6:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, $vgpr10_lo16, 0, $vgpr10_lo16, -1, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = COPY %6
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S_ENDPGM 0, implicit $vgpr0
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...
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---
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name: fold_16bit_undef_clamp
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tracksRegLiveness: true
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registers:
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: fold_16bit_undef_clamp
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
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; CHECK-NEXT: [[V_MAX_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, [[DEF]], 0, [[DEF]], -1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F16_t16_e64_]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
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%0:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%2:vgpr_32 = COPY $vgpr0
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%3:vgpr_16 = IMPLICIT_DEF
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%4:vgpr_16 = nofpexcept V_MAX_F16_t16_e64 0, %3, 0, %3, -1, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = COPY %4
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S_ENDPGM 0, implicit $vgpr0
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...
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---
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name: fold_imm16_across_reg_sequence
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tracksRegLiveness: true
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registers:
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: fold_imm16_across_reg_sequence
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B16_t16_e64_1:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_MOV_B16_t16_e64_]], %subreg.lo16, [[V_MOV_B16_t16_e64_1]], %subreg.hi16
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; CHECK-NEXT: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_MAX_F32_e64 0, -1, 0, -1, 0, 0, implicit $mode, implicit $exec
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; CHECK-NEXT: $vgpr0 = COPY [[V_MAX_F32_e64_]]
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; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0
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%0:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
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%1:vgpr_16 = V_MOV_B16_t16_e64 0, -1, 0, implicit $exec
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%2:vgpr_32 = REG_SEQUENCE %0, %subreg.lo16, %1, %subreg.hi16
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%3:vgpr_32 = nofpexcept V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
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$vgpr0 = COPY %3
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S_ENDPGM 0, implicit $vgpr0
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...
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# Make sure the immediate materialized by the v_mov_b16 isn't
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# incorrectly folded into the bfi as 0.
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# FIXME: %4:vgpr_32 = COPY %3 is a direct copy from v16 to v32 and
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# should probably fail the verifier
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---
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name: mov_v16_copy_v32_fold_b32_regression
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: mov_v16_copy_v32_fold_b32_regression
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 15360, 0, implicit $exec
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B16_t16_e64_]]
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; CHECK-NEXT: [[V_BFI_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFI_B32_e64 32767, [[COPY2]], [[COPY1]], implicit $exec
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; CHECK-NEXT: $vgpr0 = COPY [[V_BFI_B32_e64_]]
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; CHECK-NEXT: SI_RETURN implicit $vgpr0
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%0:vgpr_32 = COPY $vgpr1
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%1:vgpr_32 = COPY $vgpr0
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%3:vgpr_16 = V_MOV_B16_t16_e64 0, 15360, 0, implicit $exec
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%4:vgpr_32 = COPY %3
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%5:vgpr_32 = V_BFI_B32_e64 32767, %4, %1, implicit $exec
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$vgpr0 = COPY %5
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SI_RETURN implicit $vgpr0
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...
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