6912b91891
The prepareInsertion function was crashing when debug instructions appeared at positions being queried for slot indices. Debug instructions don't have entries in the slot index map, so getInstructionIndex would fail with an assertion. Fixes SWDEV-480902.
118 lines
6.0 KiB
YAML
118 lines
6.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
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# Test that si-wqm correctly handles debug instructions when computing
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# insertion points for SCC save/restore. Debug instructions don't have
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# slot indices, so they must be skipped when querying LiveIntervals.
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---
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# Test case 1: Debug instruction at the First position (start of region
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# requiring mode change). The pass must skip debug instructions when
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# getting slot indices to avoid assertion failure in SlotIndexes.
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name: test_debug_instr_at_first
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $m0
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; CHECK-LABEL: name: test_debug_instr_at_first
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; CHECK: liveins: $vgpr0, $vgpr1, $m0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[ENTER_STRICT_WQM:%[0-9]+]]:sreg_64 = ENTER_STRICT_WQM -1, implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DS_PARAM_LOAD:%[0-9]+]]:vgpr_32 = DS_PARAM_LOAD 0, 0, 0, 1, implicit $m0, implicit $exec
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; CHECK-NEXT: DBG_VALUE $noreg, $noreg
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; CHECK-NEXT: DBG_VALUE $noreg, $noreg
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; CHECK-NEXT: $exec = EXIT_STRICT_WQM [[ENTER_STRICT_WQM]]
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; CHECK-NEXT: S_CMP_LT_I32 0, 1, implicit-def $scc
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; CHECK-NEXT: dead [[S_CSELECT_B32_:%[0-9]+]]:sgpr_32 = S_CSELECT_B32 0, 1, implicit $scc
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; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:vreg_64 = COPY [[DS_PARAM_LOAD]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:vreg_64 = COPY [[COPY1]]
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; CHECK-NEXT: [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY2]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8)
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; CHECK-NEXT: $vgpr0 = COPY [[IMAGE_SAMPLE_V4_V2_]].sub0
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; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:vgpr_32 = COPY $vgpr1
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%2:sgpr_256 = IMPLICIT_DEF
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%3:sgpr_128 = IMPLICIT_DEF
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; DS_PARAM_LOAD requires WQM
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%4:vgpr_32 = DS_PARAM_LOAD 0, 0, 0, 1, implicit $m0, implicit $exec
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; Debug instructions after WQM instruction - become First for mode transition
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DBG_VALUE $noreg, $noreg
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DBG_VALUE $noreg, $noreg
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; Scalar compare uses SCC - causes transition from WQM to Exact
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S_CMP_LT_I32 0, 1, implicit-def $scc
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%5:sgpr_32 = S_CSELECT_B32 0, 1, implicit $scc
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; IMAGE_SAMPLE requires WQM - transition back to WQM
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undef %6.sub0:vreg_64 = COPY %4
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%6.sub1:vreg_64 = COPY %1
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%7:vreg_128 = IMAGE_SAMPLE_V4_V2 %6, %2, %3, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8)
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$vgpr0 = COPY %7.sub0
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SI_RETURN_TO_EPILOG $vgpr0
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...
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---
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# Test case 2: Multiple debug instructions after SCC use (S_CSELECT).
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# When iterating through SCC live range segments, NextI (instruction after
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# segment end) may be a debug instruction followed by more debug instructions.
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# The pass must skip all debug instructions to find a valid slot index.
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name: test_multiple_debug_after_scc_use
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_multiple_debug_after_scc_use
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr2
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr1
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_CMP_LT_I32 0, [[COPY3]], implicit-def $scc
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; CHECK-NEXT: [[BUFFER_LOAD_DWORD_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; CHECK-NEXT: [[ENTER_STRICT_WWM1:%[0-9]+]]:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK-NEXT: $scc = COPY [[COPY4]]
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; CHECK-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[COPY]], [[COPY]], implicit-def $vcc, implicit $exec
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; CHECK-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sgpr_32 = S_CSELECT_B32 [[COPY1]], [[COPY2]], implicit $scc
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; CHECK-NEXT: DBG_VALUE $noreg, $noreg
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; CHECK-NEXT: DBG_VALUE $noreg, $noreg
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; CHECK-NEXT: DBG_VALUE $noreg, $noreg
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; CHECK-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_CSELECT_B32_]], [[V_ADD_CO_U32_e32_]], implicit-def $vcc, implicit $exec
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; CHECK-NEXT: $exec = EXIT_STRICT_WWM [[ENTER_STRICT_WWM1]]
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; CHECK-NEXT: early-clobber $vgpr0 = V_MOV_B32_e32 [[V_ADD_CO_U32_e32_1]], implicit $exec
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; CHECK-NEXT: $vgpr1 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
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; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:sgpr_32 = COPY $sgpr2
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%2:sgpr_32 = COPY $sgpr1
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%3:sgpr_32 = COPY $sgpr0
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%4:sgpr_128 = IMPLICIT_DEF
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bb.1:
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S_CMP_LT_I32 0, %3:sgpr_32, implicit-def $scc
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%5:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %0:vgpr_32, %4:sgpr_128, 0, 0, 0, 0, implicit $exec
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%6:vgpr_32 = V_ADD_CO_U32_e32 %0:vgpr_32, %0:vgpr_32, implicit-def $vcc, implicit $exec
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%7:sgpr_32 = S_CSELECT_B32 %1:sgpr_32, %2:sgpr_32, implicit $scc
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; Multiple debug instructions after SCC use
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DBG_VALUE $noreg, $noreg
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DBG_VALUE $noreg, $noreg
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DBG_VALUE $noreg, $noreg
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%8:vgpr_32 = V_ADD_CO_U32_e32 %7:sgpr_32, %6:vgpr_32, implicit-def $vcc, implicit $exec
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$vgpr0 = STRICT_WWM %8:vgpr_32, implicit $exec
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$vgpr1 = COPY %5:vgpr_32
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SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
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...
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